MXPA06008913A - Scalable bus structure - Google Patents

Abstract

A processing system is disclosed with a sending component and a receiving component connected by a bus. The bus may be configured with first and second channels. The sending component may be configured to broadcast on the first channel read and write address information, read and write control signals, and write data. The sending component may also be configured to signal the receiving component such that the receiving component can distinguish between the read and write address information, the read and write control signals, and the write data broadcast on the first channel. The receiving component may be configured to store the write data broadcast on the first channel based on the write address information and the write control signals, retrieve read data based on the read address information and the read control signals, and broadcast the retrieved read data on the second channel.

Description

(17.) ZNTiSNAT.KNA APPMCATZCN? U3",: s: -: 33 JNI ??? Tl-IT, 7A77N7 CÍ? C? 7.? AT: Í? N T ??? TY (PCT) (Yes) Zzlerr.eÜo-e: Peíar .: C: ess! 2ce;! Or_7: í 1 13/0, [US / US]; 308 Bonniewood Drive, Cary, North Carolina 13/42 2751 1 (US). (?, 1) (7 <) Agsr. ,: WAI? SWGSrr: - :,?:!:!? i :, et al .; 5775 More S2OOS / 0O3789 house Drive, San Diego, California 92121 (US). (31)!? 3s! G? Ets? S etss (unless otherwise indicated, for every (27.) 3 February 2005 (03.02.2005) kind ofnatio to protection available):? E, AG,? L, AM,? T, AU, AZ, BA, BB, BG, BR, BW, BY, BZ, CA, CH, CN, (7,5) TiJiz ^ e ^ gea: English CO, CR, CU, CZ, DE, DK, DM, DZ, EC, E ?, EG, ES, 71, GB, üD, ÜK, üH, GM, HR , HU, ID, IL, IN, 1S, JP, X3, (7.5)? bl! cei: oz eg ^ ege: English KG, KP, KR, KZ, LC, LK, LR, LS, LT, LU, LV, MA, MD, MG, MK, MN, MW, MX, MZ, NA, NI, NO, NZ, OM, PG, (3C)? Rior! "Yl? Ele: PK, PL, PT, RO, RU, SC, SD, SE, SG, SK, SL, SY, TJ, TM, 60 / 542,114 4 February 2004 (04.02.2004) ) US TN, TR, TT, T, UA, UG, US, UZ, VC, VN, YU, Z ?, ZM, 10? J21,053 17? Ugust 2004 (17.08.2004) US ZW. (71) A üc pí (for all designated States except US): UA - (<) Hasíg-eied Stelzs (unless otherwise indicated, for every Morehouse Drive, kind of regional protection ava able):? RIPO (3W, GH, GM, KE, LS, MW, MZ, NA, SD, SL, SZ, TZ, UG, ZM, ZW), Eurasian (AM, AZ, 3Y, XG, KZ, MD, RU, TJ, TM), (77,). ".- vs ors; e-¿European (? T, BE, BG, CK, CY, CZ, DE, DK, EF., ES, 71, (VS) l va ~: ors / Aj ce - *. S (for US only): 1-1C7K /? N, FR, GB, GR, HU, IE, IS, IT, LT, LU, MC, NL, PL, PT, RO, S? Cierd Gere.- [US / US]; 103 Okehampton Court, Caiy, SE, SI, SK, TR), OAPI (BF, BJ, CF, CG, Cl, CM, GA, GN, North Carolina 27511 (US) .SC .-. A7773, Kz ~? VJe sC GQ, GW, ML, MR, NK, SN, TD, TG). [Continued on next page] (SQ 7!;: A: SCALABLE BUS STRUCTURE or? data ased on the read address information and the read control sign, and broadcast the retrieved read data on the second channel.

SCALABLE LINK STRUCTURE FIELD OF THE INVENTION The present disclosure generally refers to digital systems, and very specifically, to a scalable link structure.

BACKGROUND OF THE INVENTION Computers have revolutionized the electronics industry by allowing sophisticated processing tasks to be executed quickly. These sophisticated tasks can be done through systems that contain a high number of complex components that communicate with each other in a fast and efficient way using a link. A link is a channel or path between components in a computer, a computer subsystem, a computer system, or another electronic system. Many links that reside in a computer have traditionally been executed as shared links. A shared link provides a means for any number of components to communicate over a common path or channel. In recent years, technology Shared link has been implemented through point-to-point switching connections. The point-to-point switching connections provide a direct connection between two components in the link at the same time that they are communicating with each other. Multiple direct links can be used to allow several components to communicate at the same time. A common configuration for a computer includes a microprocessor with system memory. A high bandwidth system link can be used to support communications between the two. In addition, there may also be a peripheral link that is used to transfer data to peripherals. In some cases, there may also be a configuration link which is used in order to program several resources. Bridges can be used to transfer data efficiently between the upper and lower bandwidth links, as well as to provide the necessary protocol translation. Each of these links has been executed with different protocols and can have a wide variation in performance requirements between them. The use of multiple link structures in a computer has provided a feasible solution for many years. However, as the area and the energy arise as the main design considerations for integrated circuits, it is becoming more desirable to reduce the complexity of the link structure.

SUMMARY OF THE INVENTION In one aspect of the present invention, a method for initiating communication between a sending component and a receiving component on a link includes transmitting from the sending component on a first link channel read and write address information, reading and writing control, and writing data. The method also includes signaling the send component to the receiving component so that the receiving component can distinguish between the read and write address information, the read and write control signals, and the write data output in the first channel. The method further includes storing the write data output on the first channel in the receiving component based on the write address information and the write control signals, retrieving the write data of the receiving component based on the read address information and read control signals, and output from the received component the read data retrieved on the second channel.

In another aspect of the present invention, a processing system includes a link having first and second channels. The processing system also includes a send component configured to output read and write address information, read and write control signals, and write data on the first channel. The processing system further includes a receiving component configured to store the write data output on the first channel based on the write address information and the write control signals, retrieving the read data based on the information of read address and read control signals, and output the read data retrieved in the second channel to the send component. The sending component is further configured to signal the receiving component so that the receiving component can distinguish between the read and write address information, the read and write control signals, and the write data output in the first channel. In still another aspect of the present invention, a processing system includes a link having first and second channels. The processing system also includes means of sending to issue, on the first channel, reading address information and writing, reading and writing control signals, and writing data. The processing system further includes receiving means for storing the write data output on the first channel based on the write address information and the written control signals, retrieving the read data based on the address information of reading and read control signals, and output the read data retrieved on the second channel to the sending component. The sending means further include means for signaling the receiving means so that the receiving means can distinguish between the read and write address information, the read and write control signals, and the write data issuance in the first channel. It is understood that other embodiments of the present invention will be readily apparent to those skilled in the art from the following detailed description, wherein various embodiments of the invention are shown and described by way of illustration. As will be seen, the invention has the capacity for other modalities and its various details can be modified in other aspects, all without departing from the spirit and scope of the present invention. Accordingly, the figures and detailed description will be observed as illustrative in nature and not as restrictive.

BRIEF DESCRIPTION OF THE FIGURES Aspects of the present invention are illustrated by way of example, and not by way of limitation, in the appended figures, wherein: Figure 1 is a conceptual block diagram illustrating an example of a point-to-point connection on a Two-channel link between two components in a processing system; Figure 2 is a timing diagram showing a read and write operation between two components in a processing system having a point-to-point connection over a two-channel link; Figure 3 is a conceptual block diagram illustrating an example of a point-to-point connection over a high-performance two-channel link between two components in a processing system; Fig. 4 is a conceptual block diagram illustrating the time division multiplexed nature of the high performance link of Fig. 3; Figure 5 is a conceptual block diagram illustrating an example of a point-to-point connection over a two-channel low bandwidth link between two components in a processing system; Fig. 6 is a conceptual block diagram illustrating the time division multiplexed nature of the low bandwidth link of Fig. 5; and Figure 7 is a conceptual block diagram illustrating an example of a point-to-point connection between a high performance component and a lower bandwidth component through a bridge.

DETAILED DESCRIPTION OF THE INVENTION The detailed description stipulated below in connection with the appended figures is intended to be a description of various embodiments of the present invention and is not intended to represent the only embodiments in which the present invention can be practiced. The detailed description includes specific details in order to provide a complete understanding of the present invention. However, it will be apparent to those skilled in the art that the present invention can be practiced without these specific details. In some cases, well-known structures and components are shown in the form of block diagrams to avoid obscuring the concepts of the present invention. Acronyms and other descriptive terminology can be used simply by convenience and clarity and are not intended to limit the scope of the invention. Several components in a processing system can communicate over a link. The link can be scalable in terms of the width and frequency of the timer to support the bandwidth requirements of the various components. The link can also use a common architecture and signaling protocol for all scalable configurations. This can be achieved by reducing the signaling protocol of the link only to those signals needed to transmit or receive information. The link can be configured with a "transmission channel" that provides a generic means for broadcasting information from a sending component to a receiving component using the same signaling protocol in a time division multiplexed manner. A "receiving channel" can also use the same signaling protocol to send information from the receiving component to the sending component. Figure 1 is a conceptual block diagram illustrating this fundamental concept. A point-to-point connection over a link between two components is shown in a processing system. The processing system 100 may be a collection of cooperating components to perform one or more processing functions. Typically, the processing system will be a computer, or resident on a computer, and will have the ability to process, retrieve and store information. The processing system can be an independent system. Alternatively, the processing system can be incorporated into any device, including by way of example, a cell phone. In one embodiment of the processing system 100, the link 106 is a dedicated link between the sending component 102 and the receiving component. In another embodiment of the processing system 100, the sending component 102 establishes communication with the receiving component 104 with a point-to-point connection on the link 106 through a link interconnection (not shown). In addition, as those skilled in the art will readily appreciate, the inventive aspects described through this description are not limited to a dedicated link or point-to-point switching connection, but can be applied to any type of technology. link including, as an example, a shared link. The sending component 102 may be any type of link domain component including, by way of example, a microprocessor, a processor digital signal (DSP), a direct memory access controller, a bridge, a programmable logic component, a discrete door or transistor logic, or any other information processing component. The receiving component 104 may be any storage component, including, by way of example, registers, memory, a bridge, or any other component that has the ability to retrieve and store information. The storage capacity at each address location of the receiving component may vary depending on the particular application and the general design restrictions. For purposes of explanation, the receiving component will be described with a storage capacity of 1 byte per address location. The sending component 102 may be read from, or written to, the receiving component 104. In the case where the sending component 102 writes to the receiving component 104, the sending component may issue an address location, the signals of appropriate control, and the payload for the reception component 104 on the transmission channel 108. The "payload" refers to the data associated with a particular read or write operation, and in this case, a write operation.

The control signals may include transfer qualifiers. The term "transfer qualifier" refers to a parameter that describes an attribute of a read operation, a write operation, or other link related operation. In this case, the transfer qualifiers may include a "payload size signal" to indicate the number of bytes of data contained in the payload. If the payload is multiple bytes, then the receiving component 104 can store the payload in a block of sequential address locations starting with the issuing of address location in the transmission channel 108. By way of example, if the device 102 sends a 100HEX address location followed by a 4-byte payload, the receive component 104 can write the payload to a block of address locations in sequence starting at IOOHEX and ending at 103HEX- The control signals also they may include write byte enablements. "Writing Byte Enables" can be used to indicate which byte routes in the transmission channel 108 will be used to issue the payload for a write operation. By way of example, a payload emission of 2 bytes in a 32-bit transmission channel 108 may use 2 of the 4 byte routes. The write byte enablements can be used to indicate to the receiving component 104 which of the 2 byte paths on the transmission channel 108 will be used to emit the payload. In the case where the sending component 102 reads from the reception component 104, the address location and the appropriate transfer qualifiers may be the only information that needs to be transmitted in the transmission channel 108. The transfer qualifiers may include a payload size signal to indicate the number of bytes of data contained in the payload. The reception component 104 can recognize the transmission and send the payload on the reception channel 110. If the payload is multiple bytes, then the reception component 104 can read the payload from a block of address locations in sequence starting with the issuance of address location on the transmission channel 108. By way of example, if the sending device 102 issues a 200HEX address location and requests a payload of 4 bytes, the receiving component 104 can recover the payload from a block of address locations in sequence starting at 200HEX and ending at 203HEX- In the processing system mode described so far, the sending component 102 has full control of the transmission channel 108 and can emit one or more address locations with the associated control signals before, during, or after an active written operation. Also, the transmission and reception channels 108 and 110 are completely independent, and therefore, the issuance of the address, control signal and writing data by the sending component can coincide with the reading data transmission. by the reception component 104. "Write data" refers to the transmission of data by the sending component 102, and "read data" refers to the data read from the reception component 104 and emitted in the channel Reception 110. An implicit addressing scheme may be used to control the sequence of read and write data operations in the transmission and reception channels 108 and 110. By way of example, if the sending component 102 initiates multiple operations of writing by issuing a series of address locations with the appropriate control signals in the transmission channel 108, the sending component 102 will issue the payload for each write operation in the same sequence in which the locations are transmitted of direction. Similarly, if the sending component 102 initiates multiple read operations by issuing a series of address locations with the appropriate control signals, the receiving component 104 will retrieve the payload for each read operation in the same sequence in which it receives the address locations. "Transfer labels" can be used as an alternative to this implicit addressing scheme. The sending component 102 can assign a transfer label for each read and write operation. The transfer label can be included in the transfer qualifiers issued in the transmission channel 108. In the case of a write operation, the sending component 102 can send the transfer label with the payload, and the receiving component 104 can use the transfer tag retrieved from the transfer qualifiers to identify the payload. In the case of a read operation, the receiving component 104 can send the transfer tag retrieved with the payload, and the sending component can use the transfer tag to identify the payload. The various concepts so far described, are they can run using any number of protocols. In the following detailed description an example of a link protocol will be presented. This link protocol is being presented to illustrate the inventive aspects of a processing system, with the understanding that said inventive aspects can be used with any convenient protocol. The basic signaling protocol for the transmission channel is shown below in Table 1. Those skilled in the art will easily be able to vary and / or add signals to this protocol in the actual execution of the link structure described in the present invention.

TABLE 1 The same signaling protocol can be Use for the reception channel, as shown in Table 2 below.

TABLE 2 The definition of the Type field used in this signaling protocol is shown in Table 3.

TABLE 3 The definition of the valid and request transfer signals in this signaling protocol is shown in table 4.

TABLE 4 Figure 2 is a timing diagram illustrating a read and write operation on a 32-bit transmission channel and a 32-bit reception channel. A System Timer 202 can be used to synchronize communications between the sending component and the receiving component. System Timer 202 is shown with eleven timer cycles, each cycle numbered in sequence to facilitate explanation. A write operation can be initiated by the sending component during the second cycle of timer 203. This can be achieved by validating the valid signal 204 and configuring the field type 206 to signal an emission of an address location for a write operation. The address location may also be broadcast on Transmission Channel 208 to the reception component. In response to this broadcast, the receiving component stores the address location in its address queue. The issuance of the address location can be followed by a control signal emission for the write operation in the third timer cycle 205. The sending component can alert the receiving component to the emission of the control signal by maintaining Valid signal 204 reaffirmed and changing the Type 206 field appropriately. The emission of the control signal may include the transfer qualifiers and the writing byte allows the writing operation. In this case, the transfer qualifiers may include a payload size signal indicating a payload of 8 bytes. The write byte enablements may indicate that the payload of 8 bytes will be transmitted on all byte routes of Transmission Channel 208. The receiving component can determine, from this information, that the transmission of Payload will be issued on two timer cycles. The first 4 bytes of the payload for the write operation can be output over Transmission Channel 208 during the fourth timer cycle 207. The sending component can alert the receiving component to the payload emission while maintaining the Valid signal 204 reaffirmed and changing the Type 206 field to signal a payload emission. In the absence of transfer tags, the receiving component recognizes the write data as the first 4 bytes of the payload based on the implicit addressing scheme discussed above. In response to this broadcast, the first 4 bytes of the payload can be written to the receiving component. In the next timer cycle 209, the valid signal 204 and the field Type 206 remain unchanged since the second 4 bytes of the payload are transmitted on the Transmission Channel 208. However, the receiving component has invalidated the signal of Transfer Request 210 indicating that it can not accept the transmission. The sending component can detect that the Transfer Request signal 210 is not reaffirmed at the end of this fifth timer cycle 209, and can repeat the emission of the second 4 bytes of the payload in the next cycle of timer 211. The sending component may continue to emit the second 4 bytes of the payload every timer cycle until the sending component detects the assertion of the Transfer Request signal 210 of the reception component. In this case, only one repetition broadcast is required. The second 4 bytes of the payload can be written to the reception component in the sixth timer cycle. At the end of the sixth timer cycle 211, the sending component detects the assertion of the Transfer Request signal 210, and determines that the transmission has been received. A read operation can be initiated by the sending component during the seventh timer cycle 213. This can be achieved by reaffirming the valid signal 204 and configuring the Type 206 field to signal the issuance of an address location for a read operation. The address location can then be broadcast on Transmission Channel 208 to the reception component. In response to this transmission, the receiving component stores the address location in its address queue. The transmission of the address location can be followed by a control signal emission for the read operation in the eighth timer cycle 215. The sending component can alert the component of reception with respect to the emission of the control signal keeping the valid signal 204 reaffirmed and changing the field type 206 appropriately. The control signal emission may include the transfer qualifiers for the read operation. In this case, the transfer qualifiers may include a payload size signal indicating a payload of 4 bytes. The receiving component can determine, from this information, that the payload transmission can be issued during a timer cycle. Due to the read latency of the receiving component, several timer cycle delays may be experienced before the read data is available. Once the 4-byte payload is available, the receiving component can reaffirm the valid signal 212 and reaffirm the Type 214 field by signaling a payload emission on the Reception Channel 216. Because the Transfer Request signal 218 is reaffirmed by the sending component, the payload emission can be completed in a timer cycle. The reception component detects the reaffirmation of the Transfer Request signal 218 at the end of the tenth timer cycle 219, and thus determines that the payload emission was successful. Figure 3 is a conceptual block diagram which illustrates a point-to-point connection between two components on a high-performance link. The transmission and reception channels 108 and 110 of the high performance link can be executed as multiple sub-channels, wherein each sub-channel is 32 bits wide. In real executions, the number of sub-channels and the width of each sub-channel may vary depending on the performance requirements of the particular application. In this example, the transmission channel includes 4 32-bit sub-channels 108a-108d, and the reception channel includes 2 32-bit sub-channels HOa-11Ob. This execution may be convenient, as an example, for a system link on a computer, or any other high performance link. The term "sub-channel" refers to a group of cables or conductors that can be controlled independently of the other cables or conductors in the channel. This means that each sub-channel can be provided with independent signaling capability. This high performance link can be used by the sending component 102 to simultaneously broadcast various combinations of information. As an example, the sending component can issue a 32-bit address location, 32 bits of control signals including transfer qualifiers and write byte enablements, and 8 bytes of data from writing within a single timer cycle. In the case of the reception channel 110, 8 bytes of the read data can be output from the receiving component 104 to the sending component 102 within a single timer cycle. Because the various embodiments of the processing system described so far do not include some form of information transmission in the reception channel 110 other than read data, there is no need for subchannels. A single 64-bit reception channel can be executed to reduce signaling requirements (that is, not sub-channels). However, in some modes of the processing system, the Type field, in the signaling protocol, may be extended to allow the transmission of other information. By way of example, a "write response" can be transmitted on the reception channel 110 to signal to the sending component that the data has been written to the reception component 104. The write response could be emitted over the reception channel. reception 110 using one of the reserved type fields. In that case, it may be useful to have two 32-bit sub-channels independently controlled so that read data and a write response can be transmitted on the receiving channel 110 simultaneously.

With 2 32-bit sub-channels, then it may be possible to simultaneously transmit 4 bytes of read data, 2 bytes of read data and a 32-bit write response, or 2 32-bit write responses. A single 64-bit reception channel 110, on the other hand, can only support read data or write responses in any given synchronizer cycle. In a similar way, the transmission channel may also be extended to include the broadcast of other types of information that are common in many link protocols, such as standard commands. As an example, a fixed microprocessor to a link may require issuing information to other components in the system, such as a TAB Synchronization command or a TAB invalidation command. These commands can be classified in the Type field without the need for additional signaling. Figure 4 is a block diagram illustrating the time division multiplexed nature of a transmission channel 108 with 4 sub-channels 108a-108d. In this example, a full 8-byte payload transmission can be completed through the 4 sub-channels within a single timer cycle. Very specifically, during the first timer cycle 401, the sending component can transmit a 32-bit address location on the first sub-channel 108a and 32 bits of control signals in the second sub-channel 108b for the first write operation. The sending component can also transmit, during the same timer cycle, the 4 bytes of higher order of the payload in the third sub-channel 108c and the 4 bytes of lower order of the payload in the fourth sub-channel 108d . Each sub-channel 108a-108d can be provided with independent signaling capability, and in the case described above, it can reaffirm the valid signal with the appropriate Type field for each sub-channel. With the Reaffirmed Transfer Request for each sub-channel 108a-108d at the end of the first timer cycle 401, two read operations can be initiated by the sending component during the second timer cycle 403. This can be achieved by transmitting a location 32-bit address in the first sub-channel 108a and 32 bits of control signals in the second sub-channel 108b for the first read operation, with appropriate signaling in each sub-channel 108a-108b. The sending component can also transmit a 32-bit address location on the third sub-channel 108c and 32 bits of control signals on the fourth sub-channel 108d for the second read operation, again with the appropriate signaling for the sub-channels 108c-108d.

With the Reaffirmed Transfer Request for each sub-channel 108a-108d at the end of the second timer cycle, a second read operation and third read operation can be initiated by the sending component during the third timer cycle 405. This is it can achieve by transmitting a 32-bit address location in the first sub-channel 108a and 32 bits of control signals in the second sub-channel 108b for the second reading operation, with appropriate signaling in each sub-channel 108a-108b . The sending component can also transmit a 32-bit address location on the third sub-channel 108c and 32 bits of control signals on the fourth sub-channel 108d for the third reading operation, again with the appropriate signaling for the sub-channels. -channels 108c-108d. In this example, at the end of the third timer cycle 405, the Transfer Request signal is reaffirmed in the first and second sub-channels 108a and 108b, but not in the third and fourth sub-channels 108c and 108d. The sending component can detect that the Transfer Request in the third and fourth sub-channels 108c and 108d are not reaffirmed, and can therefore determine that the address location and the control signals for the third reading operation should be retransmitted. The address location and the control signals for the third reading operation are shown as transmitted during the fourth timer 407 in the third and fourth sub-channels 108c and 108d, respectively, but may be retransmitted in any sub-channel during any subsequent timer cycle. In the previous example, the receiving component is configured to either accept or reject both the address location and the control signals for the third read operation. However, in some embodiments of the processing system, the receiving component can be configured to accept the address location and reject the control signals, or vice versa, for the same read or write operation. Similarly, the receiving component can be configured to accept or reject the higher or lower order bytes of the payload individually. In this case, there is a need for a way to join a retransmission of said control signals for the third read operation to the address location for the same pre-transmission operation. This can be achieved in a variety of ways. By way of example, once an address location for a read or write operation is sent and recognized by the receiving component, the address for the next read or write operation is not transmitted until the signals controls associated with the read or write operation request are received and acknowledged by the receiving component. During the fourth cycle of timer 407, the sending component may transmit the payload for the second write operation and may attempt a second read operation a second time. This can be achieved by transmitting the upper order 4 bytes of the payload in the first sub-channel 108a and the lower order 4 bytes of the payload in the second sub-channel 108b for the second write operation, with the signaling appropriate in each sub-channel 108a-108b. The sending component may also retransmit the 32-bit address location in the third sub-channel 108c and 32 bits of control signals in the fourth sub-channel 108d for the third read operation. In this high-performance link mode, the ordering of read / write requests can be implicit by position. The sending component can transmit the first read / write request on the first sub-channel 108a, the second read / write request on the second sub-channel 108b, the third read / write request on the third sub-channel 108c , and the fourth read / write request in the fourth sub-channel 108d. The receiving component can process the requests based on this implicit positioning to maintain the sequential consistency. By way of example, if the address locations for the read and write operations initiated during the third timer cycle 405 are the same, the receiving component may wait until the data transmission on the first and second sub-channels 108a and 108b, during the fourth cycle of timer 407, is written at the address location before providing the newly written data at this address location to the receiving channel for transmission to the sending component. In the high performance link mode described so far, the written data need not be transmitted immediately after the transmission of the write operation request (i.e., the address location and the control signals). Other requests and / or higher-priority reading operation commands may be interleaved with the transmission of write data on the transmission channel 108. However, if the sending component interleaves the requests and / or read operation commands with Write data, then the sending component should be configured with an address retrace mechanism. As described above in relation to figure 2, the sending component samples the signal from Transfer Request 210 followed by a transmission in Transmission Channel 208. If the sending component does not detect a reaffirmed Transfer Request signal 210, then it may repeat the transmission during the next timing cycle. The transmission may be repeated each timer cycle until the sending component detects a reaffirmed Transfer Request signal 210. A problem may arise when the address queue is full during a read operation request, and therefore can not accept address locations. At the same time, the receiving component needs to complete the pending write operation to free space in the address queue. In this case, the reception component is said to be stagnant. The backspace steering mechanism is designed to allow the write operation to be completed when the receiving component is in stalling. This can be achieved by limiting the number of repetition transmissions by means of the sending component in connection with a read operation request. If the receiving component does not recognize a read operation request with a Transfer Request signal within a certain number of timer cycles, then the sending component you can abort the request by sending the remaining write data instead of the address location for the current read operation request. If a write operation that needs to be completed is not pending, then the transmission of the read operation request does not need to be aborted. The transmission can continue until the reception component recognizes the request. The backspace mechanism may not be necessary if the sending component does not interpolate read operation requests with write data. That is, if the address location for a write operation is immediately followed by the control signals, and then immediately followed by the write data, then the receiving component will never be stalled. However, this may degrade the performance of the reception channel because the sending component may not maintain the conduit of the read operations long enough to fully utilize the bandwidth of the reception channel. Figure 5 is a conceptual block diagram illustrating a point-to-point connection between two components over a low bandwidth link. The low bandwidth link can be executed with a single transmission channel 108 and a single reception channel 110 requiring fewer signals and resulting in less energy dissipation. In the example shown in Figure 5, the sending component 102 can transmit information to the receiving component 104 on a 32-bit transmission channel 108, and the receiving component 104 can transmit information back to the sending component 102. on a 32-bit reception channel 110. Alternatively, this same link architecture can be executed with narrower link widths. Although this configuration still allows the transmit and receive channels 108 and 110 to transmit information simultaneously, each read and write operation may now require multiple timer cycles, as shown in the block diagram of Figure 6. In this example , two timer cycles are used to start a read operation. Very specifically, a 32-bit address location can be transmitted on the transmission channel 108 in the first timer cycle 601, followed by 32 bits of control signals in the next timer cycle 603. A load can be read useful 4 bytes from the receiving component in response to this request and transmission on the receiving channel 110 in the third cycle of timer 605. Simultaneously with the transmission of the load useful in the receiving channel, the sending component can initiate a write operation. In this case, the write operation uses three timer cycles. In the third timer cycle 605, the sending component transmits a 32-bit address location in the transmission channel 108, followed by 32 bits of control signals in the fourth timer cycle 607, followed by a payload of 4. bytes in the fifth timer cycle 609. In many processing systems, some devices may require a high bandwidth interconnection while others may operate sufficiently with much lower bandwidth interconnection. When using a scalable link architecture, the execution of the bridges can be done with a common signaling protocol. Figure 7 is a conceptual block diagram illustrating a point-to-point connection between two components through a bridge. The bridge 702 can be used to interface a fixed send component 102 to a high performance link with a receive component 104 fixed to a lower bandwidth link. The high performance link can be executed with a transmission channel 108 having 4 32-bit sub-channels 108a-108d and a reception channel 110 having 2 32-bit reception channels 110a and 110b. The link of Lower bandwidth can be executed with a single 32-bit transmission channel 108 'and a single 32-bit reception channel 110'. In this example, a write operation can be completed between the sending device 102 and the bridge 702 within a single timer cycle using the 4 transmission sub-channels 108a-108d of the high-performance link to transmit the address location, the control signals, and an 8-byte payload, as previously described in connection with figures 3 and 4. The bridge 702 may buffer and transmit the information to the reception component 104 on the 32-bit transmission channel 108 'of the lower bandwidth link in 4 timer cycles, as described above in connection with the figures and 6. In the case of a read operation, an address location and the control signals can be transmitted by the sending component 102 to the bridge 702 in 2 sub-channels of the high performance link transmission within a single timer cycle. The bridge 702 can buffer and transmit this information to the reception component 104 on the 32-bit transmission channel 108 'in two timer cycles. A payload of 8 bytes can be then transmitting from the reception component 104 to the bridge 702 on the 32-bit reception channel 110 ', it can be stored in the buffer memory in the bridge 702, and then be transmitted by the bridge 702 to the sending component 102 in the two sub-stations. reception channels 110a and 110b in a single timer cycle. The various illustrative logic blocks, modules and circuits described in relation to the embodiments described in the present invention can be executed or realized with a general purpose processor, a digital signal processor (DSP), a specific application integrated circuit (ASIC) , a programmable field gate layout (FPGA) signal or other programmable logic device, discrete gate or transistor logic, discrete hardware components, or any combination thereof designed to perform the functions described in the present invention. A general purpose processor may be a microprocessor, but in the alternative, the processor may be any processor, controller, microcontroller, or conventional state machine. A processor may also be executed as a combination of computing components, for example, a combination of a DSP and a microprocessor, a plurality of microprocessors, one or more microprocessors in conjunction with a central DSP, or any other configuration. The methods or algorithms described in connection with the embodiments described in the present invention can be incorporated directly into hardware, into a software module executed by a processor, or into a combination of the two. A software module may reside in RAM memory, flash memory, ROM memory, EPROM memory, EEPROM memory, registers, hard disk, a removable disk, a CD-ROM, or any other form of storage medium known in the art. A storage medium may be coupled to the processor so that the processor can read the information from, and write information to, the storage medium. In the alternative, the storage medium can be an integral part of the processor. The processor and storage medium can reside in an ASIC. The ASIC may reside in the sending and / or receiving component, or elsewhere. In the alternative, the processor and the storage medium may reside as discrete components in the sending and / or receiving component, or elsewhere. The prior description of the described embodiments is provided to enable those skilled in the art to make or use the present invention. Several modifications to these modalities will be easily apparent to those skilled in the art, and the generic principles defined herein may be applied to other embodiments without departing from the spirit or scope of the invention. Therefore, the present invention is not intended to be limited to the modalities shown herein but will be accorded the broadest scope consistent with the principles and novel features described herein.

Claims (24)

NOVELTY OF THE INVENTION Having described the present invention, it is considered as a novelty and, therefore, the content of the following is claimed as a priority: CLAIMS

1. - A method to establish communication between a sending component and the receiving component over a link, the link comprising first and second channels, the method comprising: transmitting from the sending component on a first channel address information reading and writing, read and write control signals, and write data; sending signals from the sending component to the receiving component so that the receiving component can distinguish between the read and write address information, the read and write control signals, and the write data broadcast on the first channel store the broadcast of write data on the first channel in the reception component based on the write address information and the write control signals; recovering the write data of the reception component based on the read address information and the read control signals; and emit from the reception component the read data retrieved on the second channel.

2. - The method according to claim 1, wherein the first channel comprises a plurality of subchannels, subchannel of a first sub-channel transmits a portion of the address information during a time period concurrently with the transmission of a portion of the control signals in a second subchannel of the subchannels during the same period of time.

3. The method according to claim 2, characterized in that a third sub-channel of the sub-channels transmits a portion of the writing data during the same period of time.

4. - The method according to claim 1, wherein the read and write signals comprise a plurality of transfer qualifiers and write byte enable.

5. The method according to claim 1, characterized in that at least a portion of the reading address information and writing, read and write control signals, or write data is transmitted on the first channel simultaneously with the transmission of at least a portion of the read data retrieved in the second channel.

6. The method according to claim 1, wherein the write data comprises a plurality of payloads, and wherein the sending component broadcasts a portion of the address information reading and writing between a first and second portion of one of the payloads.

7. - The method according to claim 1, further comprising sending signals from the receiving component to the sending component to recognize the transmissions in the first channel.

8. The method according to claim 7, further comprising repeating a transmission of the same portion of the read and write address information, the read and write control signals, or the write data in response to the sending of signals from the receiving component to the sending component.

9. - The method according to claim 8, characterized in that the writing data comprise a plurality of payloads, and in where the same portion of the address information read or signals read control is repeatedly transmitted during a time period after transmission of a portion of the information write address associated with one of the payloads, but before that said payload of the payloads be completely transmitted to the receiving component, the method further comprises suspending the repeated transmission at the end of the period of time, completing the transmission of said payload, and repeating the transmission of the same portion of the read address information or the read control signals after completing the transmission of said payload.

10. The method according to claim 1, further comprising sending signals from the receiving component to the sending component to indicate the time when the receiving components are transmitting the read data.

11. The method according to claim 10, further comprising transmitting in the second channel, from the receiving component, commands and sending signals from the receiving component to the sending component so that the sending component can distinguish between the sending components. Reading data and commands.

12.- The method of compliance with the claim 11, characterized in that the second channel comprises a plurality of sub-channels, a first sub-channel transmits a portion of the read data during a period of time simultaneously with the transmission of a portion of the commands in a second sub-channel during the Same period of time.

13. A processing system, comprising: a link that has first and second channels; a sending component configured to output read and write address information, read and write control signals, and write data on the first channel; a receiving component configured to store the write data output on the first channel based on the write address information and the write control signals, retrieve the read data based on the read address information and the read control signals, and output the read data retrieved in the second channel to the sending component; wherein the sending component is further configured to send signals to the receiving component so that the receiving component can distinguish between the read and write address information, the read and write control signals, and the broadcasting signal. Write data in the first channel.

14. The processing system according to claim 13, characterized in that the first channel comprises a plurality of sub-channels, and wherein the sending component is further configured to transmit a portion of the address information in a first sub. -channel for a period of time simultaneously with the transmission of a portion of the control signals in a second sub-channel during the same period of time.

15. The processing system according to claim 14, characterized in that the sending component is further configured to transmit a portion of the write data in a third sub-channel of the sub-channels during the same period of time.

16. The processing system according to claim 13, characterized in that the read and write signals comprise a plurality of transfer qualifiers and write byte enable.

17. The processing system according to claim 13, characterized in that the sending component is further configured to transmit at least a portion of the address information of the read and write, the read and write control signals, or the write data on the first channel simultaneously with the transmission of at least a portion of the read data retrieved in the second channel by means of the reception component.

18. The processing system according to claim 13, characterized in that the writing data comprises a plurality of payloads, and wherein the sending component is further configured to transmit a portion of the read and write address information between a first and second portion of one of the payloads.

19. The processing system according to claim 13, characterized in that the reception component is also configured to send signals to the sending component to recognize the transmissions in the first channel.

20. The processing system according to claim 19, characterized in that the sending component is further configured to repeat a transmission of the same portion of the read and write address information, the read and write control signals, or the writing data in case of not receiving an acknowledgment by the receiving component regarding said transmission.

21. - The processing system according to claim 19, characterized in that the sending component further comprises a steering retraction mechanism.

22. The processing system according to claim 13, characterized in that the reception component is further configured to send signals to the sending component to indicate the moment when the receiving component is transmitting the read data.

23. The processing system according to claim 22, characterized in that the receiving component is also configured to transmit on the second channel, commands and send signals to the sending component so that the sending component can distinguish between the data of reading and commands.

24. The processing system according to claim 23, characterized in that the second channel comprises a plurality of sub-channels, the receiving component is further configured to transmit a portion of the read data in a first sub-channel during a period of time simultaneously with the transmission of a portion of the commands in a second sub-channel during the same period of time. 25.- A processing system, comprising: a link that has first and second channels; sending means for transmitting in the first channel the read and write address information, the read and write control signals, and write data; and receiving means for storing the write data output on the first channel based on the write address information and the write control signals, retrieving the read data based on the read address information and the signals of reading control, and output the read data retrieved in the second channel to the sending component; wherein the sending means further comprises means for sending signals to the receiving means so that the receiving means can distinguish between the read and write address information, the read and write control signals, and the broadcasting data. writing in the first channel.