MXPA97000206A - Interface of transportation processor and apparatus / video player in a current dedatos structured by adequate fields paratransporting televis information - Google Patents

Abstract

A system for transmitting a stream of digital data representing sequential data fields containing equal data intervals and unequal inter-data header information intervals, this system comprising: a data processor (14) for providing a stream of data at a uniform and constant data rate, a video recorder / player apparatus (15) for receiving the data stream at uniform speed from the data processor, and a data field generator (17) responding to a current of output data from the video recorder / player apparatus, to insert the header information in the unequal inter-data header intervals of the data stream, without interrupting the data stream, to form the stream of structured data in the field that represent data fields in sequence, with data intervals equal to unequal header intervals

Description

TRANSFER PROCESSOR INTERFACE AND VIDEO RECORDER / RECORDER DEVICE IN A DATA CURRENT STRUCTURED BY ADEQUATE FIELDS TO TRANSPORT TELEVISION INFORMATION Field of the Invention This invention relates to the field of digital signal processing. In particular, the invention relates to a system for facilitating the video recording / reproducing operation when processing a data stream structured by fields suitable for transporting high definition television (HDTV) information.

BACKGROUND OF THE INVENTION Recent overies in the field of video signal processing have produced high definition television digital signal processing and transmission systems. A system of these is described in the Patent of the United States of America Number: 5, 168, 356-Acampora et al. In that system, a data stream in coded words, which includes coded words compatible with the known MPEG data compression standard, is transported to a transport processor. The main function of the transport processor is to pack variable-length coded word data into packed data words. An accumulation of packed data words, called a data packet or data cell, is preceded by a header containing information identifying the associated data words, among other information. Thus an output of the transport processor is a packetized data stream comprising a sequence of transport packets. The transport packet format increases the prospects of resynchronization and recovery of signals in a receiver, for example, after a signal interruption that may be the result of a urbance of the transmission channel. This is accomplished by providing header data from which a receiver can determine re-entry points in the data stream after a loss or corruption of the transmitted data. A high definition television terrestrial transmission (HDTV) system recently proposed as the Grand Alliance HDTV system in the United States of America uses a vestigial sideband (VSB) digital transmission format to transmit a data stream packaged with a structure of prescribed data fields. The Grand Alliance HDTV system is a proposed transmission standard that is under consideration in the United States of America, of the Federal Communications Commission * "* '(Federal Communications Commission FCC) through its Committee Advanced Television Services Consultant (Advisory Commitee of Advanced Television Service ACATS). A description of the Grand Alliance HDTV system as submitted to the ACATS Technical Subgroup on February 22, 1994 (document in draft) is found in the Acts of the National Association of Broadcasters, 48th Annual Broadcast Engineering Conference Proceedings, March 20-24, 1994. In the Grand Alliance system, the data is accommodated as a sequence of data fields. Each field structure includes 313 segments: a field synchronization segment (which does not contain payload data) followed by 312 data segments. Each data segment includes a data component and a forward error correction component (FEC). A synchronization component (sync) precedes each data segment. A transport processor provides fixed length packets of 188 bytes to a transmission processor, which performs various coding functions on each packet to produce segments of output symbols to be transported to an output transmission channel. Each byte comprises a previously determined number of symbols, for example 4 symbols. The data packages contain data in accordance with the MPEG-2 data compression standard of the International Standards Organization-Images Expert Group Movement (International Standards Organization-Moving Pictures Experts Group ISO-MPEG). The transport processor provides only the data packets to the transmission processor, which adds a forward error detection and correction header header to each segment, and a field synchronization header segment at the beginning of each data field , that is, between each group of data field segments. The data flow rate must be regulated to perform these operations since, as will be seen, the components of forward error correction header and field synchronization header segment occur at different times and have different durations. The packets are separated by a range that allows the header required by each data segment (for example forward error correction data) to be inserted into the data stream by the transmission processor. However, the packet data stream must be interrupted and delayed for a period of time equal to the segment interval when the longest field synchronization segment, which does not contain a payload like the other packets, is to be inserted in the data stream. A data stream created by the need to interrupt and insert header information of different duration (correction of forward error and '"' field synchronization) at different times is illustrated in Figure 3. This data stream comprises 312 bytes of packets plus forward error correction intervals between field synchronization intervals as will be discussed.

Compendium of the Invention. The inventors have recognized that an interrupted data stream of -0 as mentioned above not only undesirably reduces the speed of data production, but also produces non-uniform intervals between data packets. The occurrence of these inter-packet intervals significantly complicates the signal processing requirements. In particular, the inventors have recognized that a stream of interrupted data undesirably complicates the interface requirements between the transport processor and the transmit processor in the transmitter, particularly with respect to data synchronization, and between any system for recording and reproduce the packed data stream. It is very likely that an HDTV data stream is subject to being recorded either by study equipment or by the consumer. To satisfy the MPEG synchronization requirements, any recording system must faithfully reproduce the synchronization of the '' * "package, including any non-uniform gap between packets, which must be maintained between the packets as the gaps are presented.This requirement significantly increases the complexity of the circuits needed to connect to a recording system. , any of these gaps caused by the transmission process must be maintained in a demodulator in a receiver The present invention is conveniently employed in the context of a system that is intended to process a packaged data stream representing a field structure of data in previously determined sequence A system according to the invention eliminates the need to align the structure of the data fields, which may be of the type exhibiting a non-uniform data rate due to different types of header information without data or of different duration as used by the Grand Alliance HDTV system as described previously . In a transmitter, a transport processor (e.g., to form data packets with associated headers) is operated at an uninterrupted constant uniform data rate in a system that inserts header information of different duration into the data stream to form the structure of sequential data fields previously determined. The processor H transport is conveniently operated at that uniform constant data rate without having to modify a previously determined original data field structure. In accordance with the principles of the invention in a transmitter, a video recording / reproducing device is placed in a constant uniform data rate data stream from the output of the transport processor. A transport processor / decoder in counterpart 0, in a receiver, similarly exhibits uninterrupted operation at a constant uniform data rate. A video recording / reproducing device is placed in a constant uniform data rate data stream in the input path of the transport processor / decoder. In a described modality of transmitter of the In the present invention, a transport processor operates at an uninterrupted constant uniform data rate in response to a SC symbol clock of 3/8 to provide 0 byte data to a buffer network at a uniform data rate The buffer writes data in response to the SC clock of 3/8 and extracts data at a non-uniform speed to a data field construction network The field construction network operates at a non-uniform data rate to produce a sequence of r * ~~ structures of output symbol fields in response to byte data and header information without data. The data field construction network requests data at non-uniform speed. The interface network converts this request into a uniform data rate request to the transport processor. A video recording / playback device is located in the path of the signal between the transport processor and the interface network. In a described receiver embodiment of the present invention, a received symbol data stream exhibits a sequential data field structure. A data field processor processes the structure of received symbol data fields at a non-uniform data rate to produce output data at a non-uniform velocity. A buffer interface network responds to a read clock SC of 3/8 to convert this data into an output stream of output MPEG bytes exhibiting a constant uniform data rate. This data stream is processed by a transport decoder which exhibits uninterrupted operation at a constant uniform data rate in response to the SC clock of 3/8 SC. A video recording / playback device is located on a signal path between the interface network and the transport decoder. f 'Brief Description of the Drawings In the drawing: Figure 1 illustrates a structure of sequential data fields including synchronization 5 (sync) and data segments. Figure 2 is a block diagram that generally illustrates an apparatus for processing a packaged data stream. Figure 3 represents a packet data stream 0 having non-uniform header intervals between the data packets. Figure 4 is a block diagram of a transmitter encoder including a buffer / interface network and a data field structuring network according to the invention. Figure 5 illustrates a channel spectrum of • "television that can be used to convey output data provided by the system of Figure 4, shown relative to the conventional NTSC television channel spectrum." 0 Figures 6-16 represent shapes waveforms associated with the operation of the transmitter system shown in Figure 4. Figure 17 is a block diagram of a receiver decoder including a baseband data processor 5 and a buffer / interface network "**" suitable for use with the video recording apparatus according to the invention, to provide output data to a transport processor. Figures 18-27 depict waveforms associated with the operation of the receiver system shown in Figure 17. Figures 28 and 29 respectively show additional details of the systems of Figures 4 and 17. s Figures 30-32 depict forms of wave useful for understanding the operation of the invention. Figures 33 and 34 respectively illustrate apparatuses as those described in Figures 4 and 17 together with a video recording / reproducing device located in accordance with the principles of the present invention.

Detailed Description of Drawings - * - Figure 1 represents a structure of data fields proposed for use by the Grand Alliance system HDTV in the United States of America, in a system to process a packaged data stream. A data stream of output symbols representing the structure of data fields is produced by a transmission processor in response to the input of data packets from a preceding transport processor. The transmission processor and the transport processor will be discussed in relationship with Figure 4. Each structure of data fields includes a synchronization segment of header fields (which does not contain payload data) preceding a group of field data segments each having an associated synchronization component. Each field data segment includes a data packet component of 187 bytes, a one-byte synchronization component as a preface to each data segment, and a forward error correction component (FEC) that follows the data. Associated with each segment is a "Y" interval that defines a data disabling interval between each data packet. The transport processor provides packets of 188 bytes of input data plus the synchronization segment to the transmission processor. The transmission processor adds forward error correction coding and field synchronization header information, and produces output segments in the form of a symbol to be transported to an output transmission channel. The synchronization component associated with each segment and the field synchronization component facilitate the acquisition of symbol packet and clock and phase blocking in a receiver under extreme noise and interference conditions. The sync component of 4 symbols is binary (2-level) to make the recovery of the clock and packet, and exhibits a pattern that repeats regularly at a single speed to allow reliable detection to a receiver under noise and interference conditions. The synchronization symbols are not encoded in Reed-Solomon or lattice nor interleaved. The field synchronization component may contain pseudo-random sequences, and serves several purposes. It provides a means to determine the beginning of each data field, and can also be used by an equalizer in a receiver as, '' - training reference signal to remove 0 intersymbols and other forms of interference. It also provides a means by which a receiver can determine whether or not an interference rejection filter is used, and can be used for diagnostic purposes such as measuring signal-to-noise characteristics and channel response. The 5 field synchronization component can also be used by phase tracking networks in the receiver to '' determine parameters of phase control cycle. Like the synchronization component, the field synchronization component is not encoded for error, 0 encoded for lattice or interleaved. In this example, the data fields do not necessarily correspond to the interlaced image fields comprising an image frame of an NTSC television signal. Figure 2 illustrates, in general, the processing of a type of data field segment 22 by the units of the transmission processor and the output processor in Figure 4. This segraento is one of the 312 segments of a data data field totaling 832 symbols. The segment illustrated by Figure 2 includes an MPEG-2 transport data packet of 187 bytes preceded by a one-byte synchronization component and followed by an associated forward error correction component containing 20 Reed-Solomon parity bytes . Each transport packet as used in the Grand Alliance HDTV system includes a 4-byte signal header, the first byte of these is a synchronization byte to facilitate packet synchronization. This can be followed by an optional adaptation header, with the rest of the package being an MPEG data payload. The one-byte synchronization component is mapped to 4 symbols before being modulated to 2 -VSB. The MPEG packet segment of 187 bytes and the coding component is encoded in 2/3 lattice and mapped to 828 symbols before being modulated to 8-VSB. The techniques for performing this modulation 2-VSB and 8-VSB are well known. A resulting output field segment 24 carried to an output channel contains a 4 symbol synchronization component followed by a data field component of 828 symbols containing MPEG data and FEC data. Figure 3 represents a data stream packaged according to the data field structure - * "~ shown in Figure 1. Each data field has 312 segments including each synchronization component, data and forward error correction, More specifically, each data field segment includes a range that spans 188 bytes of data including synchronization ("packet bytes") and an interval spanning 20 bytes of forward error correction.The 188 bytes of data of each segment are accompanied by 188 clock K intervals (cycles), and the 20 bytes of correction of forward error of each segment are accompanied by 20 clock intervals (cycles) .When it is time to insert a field synchronization segment, the data segment transmission / forward error correction should be inhibited for an interval of 228 clock cycles, which corresponds to a segment clock interval (ie, + 188 + 20 clock cycles). The synchronization segment ~ River fields contain a payload of data such as that contained in each packet data segment. This interruption of the data flow undesirably produces uneven intervals, or gaps, between the packets as shown in Figure 3. This interrupted data flow and inter-packet gaps greatly complicate signal control and hardware requirements with respect to the interface between the transport and transmission processors in both the transmitter and the receiver, and also reduces the speed of data production. Moreover, it is difficult to synchronize with the structure of data fields when playing previously recorded material. The non-uniform gaps between packages complicate the task of recording the data stream packaged in a studio or consumer recording equipment, since the gaps between uneven packages must be maintained as they are presented, that is, the recording equipment must faithfully reproduce the synchronization of. MPEG package. In addition, the uneven gaps must be maintained in an output signal produced by a demodulator in a receiver. The described problems caused by uneven gaps between packets associated with irregular header data are attacked and resolved by a system according to the present invention. In the described system a transport processor processes data packets to a - - * - constant uniform data rate in response to a clock chosen as a function of a data modulation scheme used. This clock also controls the operation of a buffer-interface network located between the transport processor and a transmission layer that processes the data according to a previously determined data field structure. An advantage of the described system is that it is not necessary to modify the original structure of data fields to achieve the operation at data rate constant uniform desired. In addition, parameters such as symbol rate, segment interleaving, Reed-Solomon error coding and synchronization components are not affected. In the transmitter system of Figure 4 according to the present invention, a transport processor 14 operates at an uninterrupted constant uniform data rate to provide MPEG byte data to a buffer-interface network 16 at a data rate uniform. The MPEG byte data path includes a video recorder / player apparatus in accordance with the principles of the present invention, as will be seen and discussed in connection with Figure 33, which will be discussed subsequently. Interface 16 provides output byte data at a non-uniform rate to a data-field construction network and encoder 17. Network 17 operates at a non-uniform data rate to produce a sequence of output symbol field structures in response to byte data and header information (forward error correction and field synchronization). The network 17 requests data at a non-uniform rate via a request signal for packets of data fields. The interface network 16 converts this request into a uniform data rate request signal (transport packet request) which is * "supplies the transport processor 14. More specifically, the transport processor 14 is included in a transport layer of the system, and the network 17 is included in a system transmission layer (also including the output processor 18) which is separated from the transport layer by the interface 16. The data source 12 includes data compression networks compatible with MPEG and provides MPEG-2 byte data to the processor - j. ^ transport 14. The transport processor 14 packages the MPEG bytes into fixed length data words that are eventually formed into fixed length data packets (188 bytes). Each packet is preceded by a header containing information that illustratively denotes the source of the program, the type of service and other information it describes and is related to the data in the payload data of the associated packet. The transport processor 14 also - inserts a 1-byte MPEG packet synchronizer at the beginning of each packet. Transmission processor 10 performs operations that include memory entry -intermediate, forward error detection-correction coding, field synchronization insertion, lattice encoding to improve carrier-to-noise ratio, interleaving to reduce the impact of data burst transmission errors, and symbol mapping. The network 17 performs a construction function of data fields in which the input data packets are formed in a structure of data fields including forward error correction and field synchronization component data as described above. Data packets are provided from the interface network 16 to the network 17 with gaps between constant uniform packets so that the data fields are formed by the network 17 without seams and without interrupting the data stream. He The transmission system of Figure 4 operates in response to a clock of symbols SC and clocks derived therefrom as will be discussed.A convenient clock frequency of symbols is 10.762237 MHz. The system described according to the present invention achieves an operation data rate of the transport processor without modifying the original data field structure, for example a field synchronization segment "" 'every 312 data segments, producing a uniform data stream using a field of 313 segments. Moreover, it is not necessary to interrupt the data stream to insert field synchronization header information between the data fields. The transmitter system of Figure 4 uses a SC-clock of 1/4 and a clock SC of 3/8 where SC is the symbol clock of the system. The choice of a 1/4 SC clock for the processing of the signal as will be seen is a result of the ** "fact that 1 byte (eight bits) comprises 4 symbols at the rate of 2 symbol bits, a SC clock of 3/8 is preferred for 8-VSB systems, while a SC clock of 3 / is preferred. 4 also within the scope of the present invention for faster data rate systems of 16-VSB In the system to be described network 16 includes a first-in-first-out (FIFO) 6 buffer between the output of the transport processor 14 and the input of the /; data field construction network 17. The packets of 0 bytes data of the transport processor 14 are extracted from the transport processor 14 and written to the buffer 46 as response to the SC clock of 3/8, and the data packets are extracted from the buffer 46 to the encoder 17 in response to the SC clock of 1/4 Both of these 5 clocks are generated by a digital machine instead of by a more expensive blocked phase cycle network. 3/8 SCs transport the processor 14 and the buffer 46 so that the data is transferred synchronously between the transport processor and the intermediate memory 0. A similar requirement applies as will be discussed. Referring to Figures 6-9, the symbol clock SC (Figure 6) and a derived synchronous clock. SC of 1/4 (Figure 7) are generated by a 5 synchronization control network 40, for example a microprocessor, in the network 17. The network 40 also generates a data field packet request signal (Figure 10) that is synchronized with the symbol clock SC since the 1/4 SC clock is used to generate the data field packet request. A synchronizer signal generator 42 in the network 16 generates the SC clock of 3/8 (Figure 8) synchronous with the SC and SC clocks of 1/4 from the synchronization network 40. Figure 9 (shown only by reference) represents a 1-byte wide pulse associated with the presence of a 1-byte synchronization pulse that appears as the first byte at the beginning of all data packets. The SC clock of 3/8 is generated by counting SC clock cycles. The unit 42 generates three output pulses for every eight SC clock pulses. Figures 7 and 8 illustrate a possible relationship between the SC clock of 1/4 and the clock SC of 3/8. Any combination of 3 clock pulses within a range of 8 clock pulses can be used to develop the SC clock of 3/8, but all three pulses must have a fixed phase relationship with the SC clock of 1/4, and the The same ratio must be maintained between the SC clock of 3/8 and the SC clock of 1/4 on the transmitter and the receiver. The illustrated configuration of the SC clock of 3/8 in Figure 8 is advantageous because this signal is easy to develop and align with the synchronization byte (which is easily detected at the beginning of each packet), and it is easy to replicate in the receiver.

Analogous observations pertain to the use of any six or eight symbol clock to generate a 3/4 SC clock, particularly for a 16-VSB signal. The illustrated relation between the illustrated clocks occurs in the synchronization control network 40. Resetting a counter at the start edge of the 1/4 SC clock that causes the packet synchronization byte to exit the buffer 46. The clock symbol is counted from 0 to 7, with 0 being synchronous H with the synchronization byte of the packet being extracted from the buffer 46. Any of three of eight SC clock numbers can be used, but the same three are also due use in the receiver / decoder. The synchronization control network 40 facilitates the generation of the structure of data fields containing 312 data segments and a field synchronization segment. The request signal packet data fields "'- * (Figures 10, 13) of the network 40 exhibits a high logic level for 188 bytes and a low logic level for 20 bytes in response to the SC clock of 1/4 The data field packet request signal of the controller 40 (Figure 10) exhibits non-uniform gaps between packets A portion of a data field is represented, specifically the last two data segments 311 and 312 of a data field, a field synchronization segment 313 at the beginning of the next data field, and the first segments of the next data field.

'This signal exhibits "enableable" data intervals when data is requested (each comprising 188 bytes of data synchronized with 188 SC clocks of 1/4), and "disabled" data intervals (each comprising 20 SC symbol clock intervals of 1/4) when the forward error correction information is to be added between the data fields. This signal displays intervals "Enabled" when data is requested (including each ? - one 188 bytes of data synchronized with 188 clocks (SC symbol of 1/4) and "disabled" intervals (each comprising 20 SC clock intervals of 1/4) when forward error correction information is to be added to the data stream, or 228 SC clock intervals of 1/4 when it is necessary to add 5 field synchronization information between the data fields. This signal is a free run input to a network of / "- system control 44 associated with the network 16. The control network 44 responds to the 3/8 SC and 1/4 SC clocks to generate an Output Package Request 0 for the Transport signal as shown in FIG. Figure 11. This signal requests a data packet of 188 bytes from the transport processor 14 every 317 ° clock cycle of 3/8 SC. This Packet Request signal contains constant uniform spaces between the requests of 5 packets to produce a uniform data rate and a uninterrupted data flow. Constant uniform spaces of 125 cycles of the 3/8 SC clock between packet requests facilitates seamless seamless insertion of header data such as forward error correction information and field synchronization between data fields within the data stream via network 17 to create the data field structure, as will be explained later. The described system deals with the processing of a "" data stream that has a field structure with 313 segments per field, consisting of a field synchronization segment followed by 312 data field segments, in this context the system described will work with multiples of the 3/8 SC byte clock, for example faster clocks including SC of 3/4, SC of 3/2, and SC of 3 in data modulation schemes that include for example 8-VSB 0 and 16-VSB. These options will be better understood after the following discussion relating Figures 10 and 11 with the Figures 30, 31 and 32. From this discussion it will also be clear that the principles of the present invention are also applicable to other types of data field structures. The waveform of Figure 10 is a constant for the modality described in the context of the data field structure of 313 segments. The structure of the waveform of Figure 11 can vary as a function of factors ** ~ as follows. Figure 30 corresponds to Figure 11, which represents the request for uniform data rate packets sent to the transport processor 14 by the network 44 in response to the byte clock SC of 3/8 for a signal of 8-VSB. If a SC 3/4 clock of twice as fast is used for the same 8-VSB modulation, the packet request for the transport processor 14 would be configured as shown in Figure 31. Since the size of each pack of data is / fixed at 188 bytes, the data packet interval remains l < f without changing to 188 cycles of the 3/4 SC clock. However, the inter-packet data disable interval has increased significantly, up to 438 cycles of the 3/4 SC byte clock. In this example, the number of cycles in each data segment has increased to 626 (double the example previous) due to the 3/4 SC byte clock of twice as fast. In other words: 626 clocks segments-188 clocks data (fixed) = 438 clocks Although the number of bytes per segment has increased, the structure of the data packet remains unchanged. The The structure of the data field also remains unchanged since each data field still comprises 312 segments each containing a data packet of 188 bytes, preceded by a field synchronization segment. Analogous observations refer to other clock multiples faster as SC of 3/2 or SC of 3, where the number of Byte clocks in the interval between data packets would grow proportionally. The SC clock of 3/8 has been found as the slowest clock to synchronize 313 bytes / segment in a data field of 313 segments. Figure 32 illustrates the use of a faster 3/4 SC clock in a higher data rate 16-VSB modulation system. The result is the same as in Figure 30. In the case of 16-VSB the symbol clock frequency (SC is doubled, and twice as many packets per unit of time are produced compared to the 8-VSB system. The byte clock data interval 188 and the disable interval between clock data of 125 bytes are the same as in the case of 8-VSB due to the relationship between the clock speed and the data rate of its type of clock. Associated modulation The slowest 3/8 SC clock is for the 8-VSB lower data rate modulation as the 3/4 SC clock is faster to the higher data rate 16-VSB modulation. It can be shown that the clock relations of desired symbols (for example, SC of 3/8, SC of 3/4, etc.) can be derived according to the following expression that relates the symbols by field: NX (188 + Y ) = S (X + 1), where X (188 + Y) and S (X + 1) both represent symbols / field; - (188 + Y) represents symbols / data segment; (X + 1) represents segments / field (for example, 313); S represents symbols / segment (for example 832); X represents data / field segments (for example 312) and represents the interval between data; and N is a factor that is going to be determined. It has been found that N is 8/3 in the case of a clock SC of 3/8 in an 8-VSB system, and it has been found that N is 4/3 in the case of a 3/4 SC clock. The transport processor 14 is synchronized by the SC clock of 3/8 to extract data, and responds to the packet request signal from the unit 44 by delivering the 188 bytes of an MPEG data packet during 188 cycles of the SC clock of 3. / 8.1 as represented by Figure 12. Figure 12 actually represents a valid data signal that is produced by the transport processor 14 simultaneously with the data packets of 188 bytes. The valid data signal exhibits the form of the packet request for the signal d «f transport (Figure 11). The packet request for data packet from the synchronization circuit 40 in the network 17 (FIG. 10) is not synchronous with the packet request signal for transport from the network 44 (FIG. 11). The data packets of the transport processor 14 (Data) are applied to the buffer 46 in the network 16 / This buffer is relatively small, with several depth packs. The buffer 46 also receives the valid data signal in a write-enabled input to allow the data packets to be written in the buffer 46 in response to the write clock SC of 3/8 (CD). The buffer 46 also receives a flag to start the packet (SOP) of the transport processor 14. This flag is generated at the beginning of every packet of data concurrent with the synchronization byte which precedes each data packet. The requests for the transport processor 14 to send a data packet to the network 17 via the interface network 16 is not answered until the buffer 46 has reached a predetermined level of filling, for example, half full. He The fill level of the buffer memory 46 is indicated by a fill flag, which is applied to a , • '-' control input of the controller 44. A data packet of 188 bytes is synchronized within the buffer 46 each 188/313 • cycles of the 0 SC clock of 3/8 (Figures 11 and 12). During the remaining 125 cycles of the 3/8 SC clock, no data is synchronized in the first-in-first-out buffer (FIFO) 46. The data input speed to the buffer 46 is uniform and exactly matches the output data rate from the buffer 46.

The output data rate is controlled by the data frame packet request signal from circuit 40. The data frame packet request signal and the packet request signal for transport no 5 are synchronous but are relate through the clock ratios of SC of 23/8 and SC of 1/4. Controller 44 contains logical networks that respond to the SC clock of 3/8, to the data field packet request signal, to the memory fill flag 1 (intermediate 5 (Figure 15) from the buffer 46, and the packet start flag (SOP) received from the supply network 45 via the buffer 46. The controller 44 provides a control signal (Figure 14) for Allowable Read (REN) entry in the buffer 46 to allow the transport packet data stored in the buffer memory to be retrieved in the , * "** network 17 at the appropriate time This occurs as follows with reference to Figures 13-16 The signal of Figure 13 is similar to the signal of Figure 10 previously mentioned.

Normally, the permissible reading signal (Figure 14) is synchronous with the request signal for packets of data fields (Figure 13). The packet start flag that normally appears at the beginning of each data packet causes the controller 44 to provide an output to the input Allowable Read from buffer 46 to stop "" "to the data extraction buffer 46. Specifically, the controller 44 is programmed to respond to the packet start flag by extracting reports from the buffer 46 for 188 bytes, then stop the extraction reports from the buffer during the forward error correction interval of 20 bytes. This allows the forward error correction network 50 in the transmission encoder 17 to calculate the information of , "error coding of the packet immediately preceding to which packet is stopped in the buffer 46. This error encoding information is inserted into the data stream during the 20-byte forward error correction header interval at the end of the preceding packet. Both the 5-Data Field Package Request (Figure 13) and the allowable buffer reading signal when presented (Figure 14) exhibit a , "'non-uniform packet gap structure required to insert the 20-byte forward error correction header information by means of network unit 50, 0, 0 and to insert the longest field synchronization header information. by unit 58. This insertion of header information is performed without interrupting the data stream.Referring to Figure 4, the insertion of the 5 field synchronization segment without stopping or interrupting "" "the data stream is facilitated by means of synchronizing the read / write of the buffer 46 in combination with the predetermined filling level of the buffer memory. Packages are written continuously in the buffer 46 from the transport processor as the packets are requested. Over a period of data fields, the exact number of bytes of data needed to constitute a data field will be transferred H of the transport processor 14 to the buffer 46. The buffer memory 46 is relatively small, in this example it is large enough to accommodate 4 data packets. The previously determined filling level of the buffer is 2 data packets, but this level may vary with the requirements of a particular system. 5 In practice, this level should be determined so that, for the known data intervals and for the intervals Disabled data in a given system, the buffer does not become saturated when the information extraction from the buffer stops to insert information of 0 header in the data stream, and does not empty at other times. When the information extraction from the buffer is momentarily halted to insert header information (eg, field synchronization) into the data stream, the data packets 5 continue to be written into the buffer to a '"*" uniform constant speed (Figure 11). During this time the buffer 46 does not fill completely. The constant uniform gap between the data packets (Figure 11) leaves enough time for the buffer 46 to be filled in while the information extraction is momentarily disabled for the header insertion. After the header was inserted during the read disabled interval, the data is extracted again from the buffer 46. During all this time the transport processor 14 has been continuously sending data packets to the buffer 46, whereby the data stream flows without interruption while the transport 14 processes data packets without interruption. When using a faster byte clock, for example of 3/4 SC or 3/2 SC, the buffer 46 does not run empty because the intervals between packets in the 8-VSB mode are longer. This allows additional time for the buffer to be re-filled from the transport processor. The Buffered Read of the buffer is also disabled by the controller 44 if the Fill flag of the buffer memory exhibits a low logic level, indicating that the buffer 46 contains less than a previously determined number of packets of ^ * ~ data. At this time the Valid Data signal of the network 44 (Figure 16) is "low" (absent) since the extraction of information from the buffer 46 has been disabled. This condition can occur, for example, when the operation of the system starts or after a system reset, for example, in the TI time. Typically the data field structure is started at the beginning of the transmission day and the transmission of data packets continues uninterrupted thereafter until the signal outside the station at the end of the transmission day. During this time, while extracting information from the buffer 46 is disabled, the transport processor 14 continues to send data packets to the buffer 46 in response to the Transport Package Request signal from the controller 44. After a predetermined number of packages has been stored and the filling condition of the buffer has been satisfied, the Fill flag (Figure 15) changes state and exhibits a high logic level. The buffer 46 again receives a Read Enable signal to take out data packets. The Enabled Read operation of the buffer memory starts at the front edge of the first enabled data interval that appears after the Fill flag is raised in response to the filling condition being satisfied. Consequently, at the moment "T2, the first byte (synchronization) of the data packet is aligned with the beginning of a packet request of the Data Field Packet Request signal (Figure 13) and with the start of the Valid Data signal (Figure 16) 5 The alignment circuit 45 in Figure 4 facilitates the operation described above illustrated by the Figures 13-16. The circuit 45 is shown in Figure 28 together with the networks 17, 42, 44 and 46 of Figure 4. The circuit of : '^ alignment 45 comprises "D" type flip-flop registers in 0 cascade 102 and 104 which are synchronized by the SC Reading Clock of 1/4 of the buffer 46 and which are enabled by the Enabled Read entry (REN) ) provided to the buffer 46 from the system controller 44. The data from the intermediate memory 46 is transported via the flip-flops registers 102 and 104 to the transmission encoder 17. The controller (- '44 produces a Read-Enabled signal in response to a Packet Start flag (a delayed version of the input packet start signal) from 0 an output of the flip-flop 102. The Start signal of Package is a delayed version in the buffer of the input of the packet start signal to the buffer 46. Continuing with Figure 4, the output of packets 5 of 8 bytes parallel data of the network 45 and the signal of Data • • - Valid (Figure 16) apply to respective inputs of the forward error correction unit 50 in the transmission encoder 17. The forward error correction unit adds 20 bytes of forward error correction data to the data stream during the "invalid" data header ranges between each data packet interval according to the waveform of Figure 16. The data stream from the forward error correction unit 50 is applied to the serial parallel data converter 52. The unit 52 converts each 8-bit byte into a group of four 2-bit words that are output in series. Using well-known techniques, the data of unit 52 is encoded in 2/3 lattice by unit 54 to produce three output bits (two information bits and one redundancy derived bit) for each two input bits to improve the performance of signal against noise. These bits are provided according to a predetermined algorithm, examples of which are known in the art. The encoder 54 operates together with the bit generating unit 56, which provides the third bit according to the previously determined algorithm. The output of the lattice encoder 54 comprises a sequence of words coded in 3-bit lattice, four words consisting of 3 bits one byte. The symbol mapper 58 maps each 3-bit input word from H ~ the encoder 54 to an output symbol, and multiplexes these output symbols in time with a predetermined value field synchronization component from the unit 60 to produce a symbol data stream exit. In the mapping function of unit 58, eight binary output values numerically increasing progressively from unit 54, from 000, 001, 010, ... to 111, are translated into the following eight levels of • * - 'symbols, respectively 10 -7 -5 -3 -1 +1 +3 +5 +7. The control signals for the field synchronization generator 60 and the mapper 58 are provided by the synchronization control network 40, for example, a microprocessor. The network 40 controls the operation of the field synchronization generator 60 so that unit 60 is enabled to extract information from segments * • '- • field synchronization during a pre-determined duration interval produced between adjacent data fields, ie after each 312 data segments as discussed. Each field synchronization segment is predictably multiplexed in the data stream between the field data groups without interrupting the data flow, as previously discussed with respect to the operation of the buffer 46. The multiplexer 58 also replaces the MPEG sync component to - * "'start of each packet with a synchronization segment before the output processing by the unit 18. An 8-level symbol data signal from the unit 58 is provided to the output processor 18, where 5 can be added a small pilot signal to a suppressed radiofrequency carrier to allow recovery of a robust carrier in a receiver under difficult reception conditions Using known signal processing techniques, an 8-VSB modulator in the processor 18 receives the 0 signal of composite data encoded in lattice, filters and spectrum forms the signal for transmission over a standard 6 MHz television channel, modulates (converts upward) the data signal in an intermediate frequency carrier, and translates the resulting signal to a radio frequency carrier 5. Figure 5 represents, in the diagram above, the spectrum of the band modulation signal "- vestigial baseband side for this example, in relation to the standard 6 MHz NTSC channel spectrum as shown in the diagram below .. Figure 17 depicts a vestigial sideband receptor embodying the principles of the present invention. A data stream of baseband demodulated symbols from a preprocessor 72 exhibits a sequential data field structure as described above, with a non-uniform data rate.

Data 75 associated with a transmission layer of the system processes the structure of symbol data fields with a non-uniform data rate to produce output data at a non-uniform velocity. An intermediate memory interface network 84 converts this data into a stream of MPEG byte data that exhibits a constant uniform data rate. This data stream is processed by a transport decoder 86 which exhibits uninterrupted operation at a constant uniform data rate 0 to provide decoded byte data to an output processor 88. The transport decoder 86 is associated with a layer system Of transport. The MPEG byte data path includes a video recorder / player apparatus in accordance with the principles of the present invention, as will be seen and discussed in connection with Figure 34, which will be discussed subsequently. • - More specifically, a signal received from a transmission channel is processed by a radio frequency tuner 70 that includes channel selection and 0 mixing circuits to produce a down converted frequency signal. This signal is subjected to intermediate frequency filtering and synchronization detection by the preprocessing unit 72 using known signal processing techniques to produce a baseband signal. 5 the unit 72 also includes an equalizer to compensate the amplitude of transmission channel and phase disturbances. A symbol data output signal from the unit 72 is then subjected to lattice decoding, error detection / correction and other signal processing in a manner that is the inverse of the processing performed by the transmitter system of Figure 4. The SC symbol clock and SC 1/4 and SC 3/8 derivative clocks are identical to the corresponding • clocks in the transmitter. Thus an output data stream (MPEG byte data) provided to a transport processor / decoder 86 corresponds to the data stream (MPEG byte data) provided from the transport processor 14 in the transmitter system of Figure 4. The symbol data applied to the symbol mapper and the demultiplexer unit 74 corresponds to the output symbol data of the network 17 in Figure 4. The input symbol data stream contains a relatively long field synchronization component. duration between groups of data packets of shorter duration that respectively define adjacent data fields (Figures 1 and 3). Thus the input symbol data stream of the receiver exhibits a non-uniform data rate. Before being applied to the receiver transport processor 86, this non-uniform velocity input symbol data stream becomes an output signal of r - MPEG byte data (from network 84) containing data packets that are presented at constant uniform data rate separated by uniform gaps between packets. This uniform rate constant data stream 5 advantageously facilitates data processing and data demultiplexing by transport decoder 86, which operates without interrupting the data stream. /, More specifically, a stream of data from l? Non-uniform velocity baseband input symbols produced after demodulation and equalization are applied to the symbol mapper and demultiplexer 74, which performs the inverse of the operations performed by the mapper 58 in Figure 4. Unit 74 maps each symbol to a word of bits that are decoded by lattice to a 2-bit word by the lattice decoder 76 together with the unit 78. The unit 74 also replaces the synchronization segment at the beginning of each segment packet with an MPEG packet synchronization. A stream of data from The symbols processed by the unit 74 are monitored by the unit 90 to detect the occurrence of control information present during the field synchronization intervals, for example, the information called "training" signal for use by a preceding equalizer in the unity 72, the mode selection information and other information.

• 'This information is extracted through unit 90 and transported to the preceding circuits according to the requirements of a particular system. The output groups of four 2-bit data words from the lattice decoder 76 are converted from the serial form to the 8-bit parallel form (1 byte) by the serial to parallel converter 80. The serial words from the converter 80 are applied to the error detection and correction unit 82, for example a Reed-Solomon decoder. A corrected error data signal from the unit 82 is applied to the buffer network / receiver interface 84 together with a valid data signal, the SC and SC clocks of 1/4, and the packet start signal from the controller 92. The SC symbol clock and the 1/4 SC clock are synchronized and are produced by a local oscillator in the controller 92. The packet start signal is generated in response to the appearance of the synchronization byte at the beginning of the each package. The forward error correction unit 82 generates the valid data signal in response to the packet start signal. The buffer network / interface 84 is similar to the transmit network 16 and is shown in Figure 29. The interface network of Figure 29 includes a first-in-first buffer FIFO 100, a system controller 120 , a SC clock generator of 3/8 122 and a r ~ alignment circuit 145, all of which elements exhibit characteristics similar to their counterpart elements of the transmit network 16 shown in Figure 28. The buffer 100 of Figure 29 is essentially the same as the first-in-first buffer at exit 46 in the transmit buffer network 16 in Figure 4, except that the Read and Write clocks are exchanged. Specifically, the input of the write clock WCK of the buffer 100 responds to the clock SC of 1/4, and the input of the Read clock RCK of the buffer 100 responds to the clock SC of 3/8. In Figure 29 the packet start input signal for the register 110 is a buffered version of the packet start signal, and the packet start input to the transport processor 86 is a delayed version of the input from packet start to register 110. Continuing with Figure 17, a baseband MPEG byte data stream packetized from network 84 is processed by a transport / decoder processor 86, which basically performs the inverse of the operations made by the transport processor 14 in the transmitter (Figure 4). The transport processor 86 decodes data into its constituent components. Processor 86 includes several data processing and demultiplexing circuits that include header analyzers, router routers, f signals that respond to header information, MPEG decompression networks, and other audio data processors that provide signals that are formatted as required by the video / audio processor in Figure 17. The video and audio data retrieved by the transport decoder 86 are respectively processed by the video and audio networks in a unit 88 to provide image and sound information suitable for their reproduction. The detector 90 in the network 75 also provides a field marker signal to control the unit 92. The field marker instructs the controller 92 not to write the field synchronization segment in the buffer network 84, while a The resulting output data stream is emptied of the field synchronization component. The output data packets from the buffer network 84 form a single data stream that is empty of the field synchronization component whereby the MPEG byte data stream from the network 84 exhibits a uniform, constant data rate. , and gaps between uniform, constant packages. Removing the header field synchronization segment without stopping or interrupting the data stream is facilitated by the way of synchronizing the read / write of the buffer 84 in combination with the filling level of the previously determined buffer. The t packets are continuously extracted from the buffer 46 to the transport processor as packets are available. In a data field period, the exact number of bytes of data needed to constitute a field of data data will have been transferred to the transport processor 86 from the buffer 84. The buffer 84 presents the same size and requirement for filling the buffer 46 in the transmitter. When reading from ,. the buffer 84 is momentarily disabled for L to remove header information (e.g., field synchronization) from the data stream, the data packets continue to be drawn to the transport processor 86 at a constant uniform rate. During this time the buffer 84 does not empty completely. The constant uniform gap 5 between the data packets allows sufficient time for the buffer 84 to be partially emptied while the script is momentarily disabled to remove the header information from the data stream. After the information of 0 header has been removed during the write interval disabled, the data is again written to the buffer 84. During all this time the transport processor 86 has been continuously receiving data packets from the buffer 84, whereby the data stream flows without interruption while the < "transport 86 processes data packets without interruption.The waveforms shown in Figures 18-27 refer to the operation of the receiver.The clock synchronization in the receiver is achieved through the use of the packet synchronization byte, which it was previously explained in the first byte of every data packet, as in the case of the transmitter, after capturing the synchronization byte at the beginning of a packet (Figure 21), a symbol clock SC (Figure 18) and a clock are generated. 1/4 SC mutually synchronized (Figure 19) Also compliant on the transmitter, a counter is used to count SC clock cycles of 1/4 to produce the SC clock of 3/8 of the receiver (Figure 20). is reset to zero synchronously with each packet sync byte The observations made above with respect to the structure and characteristics of the 3/8 SC symbol clock on the transmitter also apply to the SC clock of 3/8 on the The SC clock of 1/4 and the SC clock of 3/8 must be identical on the transmitter and on the receiver. Figure 22 illustrates the synchronization signal of valid output data produced by the unit 82 of the network 75 concurrent with the data signal of the processor 75. The shape of the valid data signal corresponds to the shape of the data signal of the processor 75. This valid data synchronization signal exhibits a non-characteristic / * "* uniform with gaps between non-uniform packages, including a hollow 20 (clock) accounts corresponding to forward error correction data inserted into the data signal, and a significantly wider gap, of 228 accounts 5 corresponding to synchronization of fields in the data signal The data packets in the data signal appear during the intervals of 188 counts filled to the positive of the valid data signal Thus, the data signal of the network 82 exhibits a flow of non-uniform data with respect to the packet data 0 The counterpart of the valid data signal of the Figure 22 on the transmitter is shown in Figures 3 and 10. In contrast, the valid data signal provided from the buffer network 84 to the transport / decoder processor 86 (Figure 23) exhibits a uniform structure with uniform gaps between packages. This signal means that the MPEG byte data stream from -, the network of the buffer 84 is constituted by gaps between constant uniform packets ("disabled data" intervals of 125 SC clock counts of 3/8) between 0 constant uniform data packets ("data enabled" intervals of 188 SC clock counts of 3/8). Thus the MPEG byte data data stream exhibits a constant uniform data stream to facilitate the uninterrupted operation of the transport processor 86. In response 5 to the valid data signal of Figure 23, the processor of r "transport 86 acquires data packets to process during each 188-count clock interval based on an uninterrupted flow of data." The transmitter counterparts of the valid data signal of Figure 23 are shown in the Figures 11 and 12. The buffer network / receiver interface 84 operates in a manner similar to that of the counterpart transmitter network shown in Figure 28. As noted - 'previously, first-in-store buffers first out (FIFO) respective differ with respect to the read and write clock inputs. Also while the controller 44 of the transmitting system in Figure 28 provides a packet request signal for transport in response to the data field packet request, the The receiving counterpart network in Figure 29 sends a packet start flag to the receiving transport processor 86 r ~~ to indicate the start of a new packet. As in the case of the buffer 46 of the counterpart in the transmitter, the buffer 100 of the receiver in the figure 29 is emptied and filled to a predetermined level each time the receiving system is restarted. The buffer 100 must reach a predetermined level of "filling" before the data is allowed to be extracted. This operation is illustrated by the Figures 24-27 and is analogous to the related operation of the f transmitter previously described with respect to Figures 13-16. The controller 120 generates an internal free run synchronization waveform shown as dotted lines in Figure 24. This signal exhibits a constant uniform structure. Specifically, this signal is constituted by constant uniform intervals of 125 counts of the SC clock of 3/8 (corresponding to the - disabled intervals of data between packets) between constant uniform intervals of 188 SC clock counts of 3/8 (corresponding to the data packet data enableable intervals). From this the signal controller 120 produces a first-in-first-out-of-first-out-of-the-way (Figure 25) for buffer 100 and the valid data signal (Figure 27) for transport processor 86, both with a constant uniform structure. * -. These signals are produced in response to the buffer filling signal (Figure 26) and the entry of the packet start flag in register-110. This flag is a delayed and buffered version of the signal from packet start, the packet start (delayed register) output of the register 110 is applied to the control input of the unit 120 and the transport processor 86. The buffer filling signal occurs when the buffer memory 100 exhibit ; a previously determined filling. The Buffer Enableable Read operation starts at the leading edge of the first enableable data interval (going towards the positive) that appears after the signal from filling goes up in response to the filling condition of the buffer is satisfied.

Consequently, at time T2, the first byte (synchronization) of the data packet is aligned with the < - < start of a valid data range of the valid 0 data signal (Figure 27). Both the flip-flops and the reading clock (RCK) input of buffer 84 are synchronized by the same SC clock of 3/8 locally generated by unit 122 in response to clocks SC and SC of 1/4. as discussed previously. The 3/8 SC clock also applies to the controller 120. The MPEG byte data is conveyed via the flip-flops 110 and 112 to the data input of the transport processor 86 when these flip-flops are enabled by the signal of Enabling reading produced by control 120. At the same time, the packet start flag is transported to transport processor 86 together with the valid data signal (Figure 27) from controller 120. The valid data signal is supplied to the transport processor 86 to allow it to acquire data during 5 intervals when valid packet data is present.

The interface between the transport processor and the transmission processor that includes the network 17 is important in many applications. In television broadcasting for example, the transmission processor will be required to generate 5 and produce data fields without interruption as soon as transmission has begun. Television receivers depend on this uninterrupted stream of data fields that include field synchronization segments for r * "to maintain synchronization. Any change in speed of data fields or structure during broadcasting would result in a loss of synchronization in a receiver. A transmission studio usually has multiple banks of pre-programmed video tape players to automatically switch to the appropriate source material. in a synchronized manner. These video players produce transport packages that contain information in transport stream. Each tape player synchronizes its output with the data stream to the transmission processor, which is not allowed to alter its field speed or structure of field. The non-uniform gaps in the packet flow from the transport processor to the transmission processor have the effect of making the structure of transmission data fields an artifact in the data stream in the interface, which would have both a packet and a packet. a data field structure. Each studio recorder was / would undesirably require him to have complicated interfaces that would synchronize the output of the tape both towards the boundaries of the packet and the field. It would require additional information about the field structure to pass through the interface, or to develop it by monitoring the flow of data in the interface. The tape interface would contain provisions for detecting packet synchronization, field detection and sufficient memory to buffer the data field structure. Other additional complications are produced by tapes recorded previously, and the insertion of local and commercial programming. These complications and other difficulties are successfully solved by a recording / reproducing system employing the principles of the present invention as shown in Figures 33 and 34. Figures 33 and 34 respectively represent the transmitter and receiver systems shown in Figures 4. and 17, except that the systems of Figures 33 and 34 include a video recording device. In Figure 33 a video cassette recorder / player device 15 receives a uniform data rate data stream from a transport processor 14, a reproduction data is provided at a uniform rate to the encoder and field construction network. data 17 via the buffer / interface 16. As in the case of the system of Figure 4, the system of Figure 33 exhibits a uniform data flow at the interface between the transport layer and the transmission layer. In this example the data source 12 includes a broadcast studio video camera and an MPEG encoder for encoding the output signals of the camera before packaging them by the transport processor 14. The video recorder 15 can be a commercial device as a Panasonic ™ D3 video tape recorder to provide byte-by-byte recording to the tape. In some designs of video recorders the interface 16 can be included in the same recorder device, the recorder 15 can comprise one of a bank of several video recorders commonly employed in broadcasting studios as they are known to facilitate the transmission of several types of study program material. In Figure 34 a video cassette recorder / player device 85 receives and processes a uniform data rate data stream (with header information removed) from an interface / buffer 84, and provides reproduced data at a uniform rate to a transport / decoder processor 86. The system of Figure 34 also exhibits a uniform data flow at the interface between the transmission layer and the transport layer. In this system the recorder 85 represents a consumer device (VCR) capable of recording out of the air, or for reproducing material as previously recorded by a device having the characteristics of unit 15 in Figure 33. Unit 85 may be a unit separated in a system where elements 72, 75, 84 and 86 are incorporated into a television receiver. Alternatively, elements 72, 75, 84 and 86 can all be included in the recorder 85.

Claims (9)

r CLAIMS

1. (A system for transmitting a stream of digital data representing fields of data in sequence containing equal data intervals and unequal inter-data header information intervals, this system comprising: a data processor (14) to provide * a current of data at a uniform and constant data rate, a video recorder / player apparatus (15) for receiving the data stream at uniform speed from the data processor, and a data field generator (17) responding to a output data stream from the video recorder / player apparatus, to insert the header information in the unequal inter-data header intervals of the data stream, without interrupting the data stream, to form the structured data stream in the field representing the data fields in sequence, with equal data intervals and unequal header ranges.)

2. A system for A stream of digital data representing sequential data fields containing equal data intervals and intervals of "unequal inter-data header information, this system comprising: a data processor (72, 75) that responds to the stream of structured digital data in the received field 5, to remove the header information from the data stream without interrupt the data stream; an element (84) for transporting an output data stream from the data processor to a,. output terminal at a uniform data rate and constant 0; and a video recorder / player apparatus for receiving a data stream having a uniform and constant data rate from the output terminal.

3. A system according to claim 2, wherein: the data stream is compatible with MPEG. A system according to claim 2, and further comprising: a data decoder (86) that responds to 0 an output data stream from the video recorder / player apparatus, and operates at a data rate uniform and constant, to provide a data stream of a uniform data rate decoded output without interruption. 5. A method to record a video signal in a "J" system for receiving a stream of structured digital data in the field, representing sequential data fields containing equal data intervals and unequal inter-data header information intervals, this method comprising the steps of: (a) removing (75) the header information from the data stream, without interrupting the data stream, to produce a data stream with a non-uniform data rate, and (b) transporting (84) the data stream produced by the data stream. processing step (a), to a recording / reproducing apparatus, at a uniform and constant data rate 6. A method according to claim 5, which comprises the additional step of: (c) decoding (86) the output data from the recording / reproducing apparatus in step (b), at a uniform and constant data rate, without interruption 7. A method according to claim 5, wherein: the data stream is compatible with on MPEG. 8. A system for transmitting a stream of digital data representing sequential data fields containing equal data intervals in unequal inter-data header information intervals, this system comprising: a data processor (14) for providing a data stream at a uniform and constant data rate; a video recorder / player apparatus (15) for receiving the data stream at a uniform speed from the data processor, - a data field generator (17) responding to an output data stream from the recording apparatus / video player, to insert the header information in the unequal inter-data header intervals of the data stream, without interrupting the data stream, to form the structured data stream in the field representing sequential data fields, with equal data intervals and unequal header ranges; and a modulator that responds to the data stream from the data field generator, to produce a signal modulated in vestigial sideband (VSB) for transmission; wherein: the header information includes data header information and field synchronization header information, which occupy respectively header ranges of an unequal duration. 9. A system according to claim 8, wherein: the stream of structured data in the field comprises a sequence of fields, each including: (a) a plurality of data segments, each including a data range and a data header range, and (b) a field synchronization segment containing the field synchronization header information preceding the plurality of data segments. SUMMARY A high definition television signal 5 transmitted is represented by a packet data stream configured as a sequence of data fields (Figure 1) with a non-uniform data rate due to intervals of inter-data header information - < -, unequal. Each data field is preceded by a field synchronization header segment 0, followed by 312 packetized data segments, each with associated header information (FEC). In a transmitter (Figure 33), a transport processor (14) forms data packets with associated headers, and exhibits an uninterrupted operation at a uniform and constant data rate, while supplying a packet data stream to a network (17), • 'which constructs data fields in sequence by inserting header information that is not data in the data stream. The transport processor 0 is conveniently operated at a uniform and constant data rate without having to modify the structure of the original data field to accommodate the needs of the construction network of the data field. This result is facilitated by the transfer of data from the transport processor to an interface / memory area network associated intermediate (46) in response to a 3/8 symbol clock, in combination with a previously determined buffer zone fill level. Specifically, a video recorder / player device (15) receives a packetized data stream at a uniform and constant data rate from the transport processor, and produces a data stream at a uniform and constant data rate towards the data stream. interface network / memory _ • -. *. intermediate. A transport processor / decoder (86) at 0 counterpart in a receiver (Figure 34) coact with a data field processor (75), and similarly exhibits uninterrupted operation at a uniform and constant data rate. A video recorder / player device (85) receives a data stream at a uniform and constant data rate 5 from an interface / buffer (84) after removing the header information, and * produces a stream of data at a time. uniform and constant data rate towards the transport decoder. 0 * * * * *