MULTIPLE VIDEO ENTRY FIXING ARRANGEMENT
The present invention relates generally to video processing systems, and particularly to video signal clamping circuits for use in video processing systems. The information represented by a composite television signal is defined by a luminance component, and additionally a chrominance component, in the case of a color video signal. A brightness reference level is contained in a black level of the luminance component, and any variations in this level of direct current result in undesirable variations in brightness of the image. In a video signal processing system having multiple video input signals, the change of the selected input video signal will result in undesirable image brightness variations (e.g., flash image) if the black level of the old and new entry signs are different. Additionally, in a video signal processing system, such as a television system, having the ability to visually display an auxiliary or secondary image as well as a main image, such as in an image-in-image (PIP) system , it is desirable that the brightness levels of the main and secondary images be approximately equal. Video processing systems capable of displaying secondary and main images visually can allow the individual selection of a number of different video input signals to be visually displayed either as the main or secondary image, making it even more difficult to balance the brightness of the video. the picture. To avoid black level differences in a multiple input system it is known that a reference level is held, such as the black levels or peaks of the synchronization pulses ("synchronization tips") of the synchronization intervals of all the video input signals at a common reference level. Errors in signal processing may occur even when all video input signals are subject to a common reference signal. For example, if a synchronization signal separator is used that includes a level comparator ("synchronization splitter") to extract the synchronization components, the phase shifts in the signal processing channel between the input switch and the output separator synchronization, will introduce errors. Such errors occur whether the signal processing channel is analog or digital. Feedback can be used from the output of the signal processing channel to the clamping circuit to reduce clamping errors. A similar feedback fastener is described in U.S. Patent No. 4,197,557 (Turna et al.). In Figure 2 a digital feedback clamping circuit of the prior art is shown. This digital feedback clamp will clamp the direct current level of an analog / digital converter output to a level determined by a digital comparator. Unfortunately, such known feedback clamping arrangements are only operative on a single video input signal. Accordingly, in a multiple input video signal processing system, unselected video input signals will not hold at the same direct current level as the selected video input signal. As such, this circuit arrangement is susceptible to undesirable image brightness variations during the input reselection and during the simultaneous visual display of main and image-in-image images, as described above. The present invention concerns a video signal holding apparatus having a first mode of operation for holding an input signal to a first reference level, a second mode of operation for holding a signal derived from the input signal to a second reference signal, and an element for selecting the mode of operation. Illustratively, the present invention allows a video signal processing system having multiple video inputs, a video processing channel for selectively holding a video input signal, using a predetermined direct current reference level. , or a direct current reference level derived from the output signal of the signal processing channel. Accordingly, a selected video signal can be clamped to the direct current reference level derived from the output of the signal processing channel, and an unselected signal can be held at the predetermined direct current reference level. The brightness variations are reduced because both video input signals, the selected one and the unselected one, are subject to direct current reference levels. The present invention will be described with reference to the accompanying drawings, in which: Figure 1 shows a multiple video input television system, including a signal holding apparatus embodying the present invention. Figure 2 shows a prior art signal clamping apparatus, which is employed as part of an embodiment of the present invention, in accordance with another aspect of the present invention. Figure 3 shows a multiple video input television system, including a signal holding apparatus embodying the present invention. Figure 4 shows a converter circuit
Analog / Digital suitable for use with the television systems of Figures 1 and 3. The same reference designators in the different Figures refer to the same or similar elements. Referring to Figure 1, a video signal processing system, illustratively a television system, includes N video inputs, although only two, 101 and 201, of the N inputs are shown. The video input signals Composite first CVl and second CV2 are coupled by respective capacitors Cl and C2, to switch 300 and switch 400. Capacitors Cl and C2 include respective output nodes 102 and 202. The output nodes 102 and 202 of the capacitor are coupled to respective clamping circuits to control the direct current levels of the signals present at the output nodes of the respective capacitor. The elements 100 and 200 comprise portions of the clamping circuits for CVl and CV2. In Figure 1 is shown as 200, a portion of the clamping circuitry that is used to control the direct current level for the CV2 input signal. The television system of Figure 1 includes a main image processing channel and an image-in-picture (PIP) processing channel. When a video input signal is selected for image-in-picture processing, the selected video signal is held by the clamping arrangement at a direct current reference level derived from the selected input signal, after the image-in-image processing channel has processed this, in order to reduce phase shifts due to processing. However, even when the image-in-picture processing channel does not select a video input signal for processing, the direct current level of the unselected video signal is subject to a direct current reference level of such that the subsequent selection of the video signal will not result in undesirable variations in the brightness of the image. The main processing channel • includes a switch 400, which responds to a controller 350, for selectively coupling one of the N video input signals to an analog to digital converter 410. The Analog / Digital converter 410 converts the video signal from selected input in an 8-bit data stream which is presented to a comb filter 420 for processing within separate digital data streams of luminance DYM and DCM chrominance. The digital data streams of luminance DYM and chrominance DCM are converted into respective analog signals of luminance AYM and chrominance ACM by the respective digital-to-analog converters 430 and 440. After the main analog signals of luminance AYM and chrominance ACM are coupled to a first pair of input terminals of a switch 500. The image-in-picture processing channel includes a switch 300, responsive to a controller 350, for selectively coupling one of the N video input signals to an analog to digital converter 310. The Analog / Digital converter 310 converts the selected input video signal into an 8-bit data stream which is presented to a digital signal processor (DSP) 320, and to a digital 360 comparator. The digital signal processor 320 is responsive to the controller 350 for processing the digital video data stream, to produce a stream of luminance data DYP digital data and a DCP digital chrominance data stream representative of the secondary or small image. The digital signal processor 320 reduces the size of the image represented by the secondary video signals of luminance and chrominance, by means of the suppression of pixels and lines of these components. The digital data streams of luminance DYP and chrominance DCP are converted into respective analog signals of luminance AYP and chrominance ACP, by the respective digital converters to analog 330 and 340. Then the analog luminance image-in-picture signals AYP and ACP chrominance are coupled to a second pair of input terminals of the switch 500. The switch 500, which is responsive to the controller 350 operating in a "main" mode, couples only the main analog signals of luminance AYM and chrominance ACM to a processor 600 of luminance and chrominance. The luminance signal is processed to control the contrast, sharpness and brightness properties of the image. The chrominance signal is demodulated to produce signals of red color difference R-Y, green G-Y and blue B-Y, and is processed to control the saturation and dye properties of the image. The processed luminance signal Y and the color difference signals RY, GY, BY are coupled to an output and matrix amplifier or "driver" 700, which supplies high-level red signals R, green G and blue B to a device display 800. The switch 500, which responds to the controller 350 operating in an "image-in-picture" mode, additionally couples the analog luminance image-in-picture signals AYP and ACP chrominance to the luminance processor 600 and chrominance, during a predetermined portion of the main image, such that the video signal processed by the image-in-image processing channel is displayed visually as a small image inside the larger main image, by the device of visual display 800. The fastener 100 receives a reference signal CLAMP_REF1, a switch control signal ADC_FB, and a selection signal USE_ADC_FB1. Similarly, the fastener 200 receives a reference signal CLAMP_REF2, a switch control signal, which is the same as ADC_FB, and a selection signal USE_ADC_FB2. The rest of the description will refer mainly to the fastener 100, since the fasteners 100 and 200 are similar. The respective reference signals CLAMP_REF1 and CLAMP_REF2 are direct current voltage levels. These voltage levels can be from different voltage sources or a common voltage source. The purpose of the respective reference signals CLAMP_REF1 and CLAMP_REF2 is to set the clamping levels for respective video signals, which are not selected for processing by the image-in-picture video processing channel. In exemplary mode, the switch control signal ADC_FB is produced by the image-in-picture video processing channel. This switch control signal is derived, for example, by comparing the output of an Analog / Digital converter 310 with a digital word representing a direct current signal reference level, for example, corresponding to the peak level of synchronization. The purpose of the ADC_FB switch control signal is to set the clamping level for a video signal that is selected for processing by the image-in-picture video processing channel. Controller 350 produces the selection signal USE __? DC_FB. T »n control of the controller 350 no, ori t í <; -; for the present invention; It may comprise a microprocessor or microcontroller, a multiple state, a combination logic circuit, or an analog control circuit. Controller 350 may also incorporate a user input, for example, remote control input (s). The fasteners 100 and 200 have two modes of operation; a primordial mode (not r.oln cioníi íi) ro ur.a pnrn hold inputs that the channel of slow process of image-in-image video does not select for processing, and a second mode (selected) is used to hold selected inputs for image-in-image processing. The unselected and selected mode are determined by, respectively, a high logical and low logic level of the reference selection signal USE_ADC_FB. In the illustrated embodiment circuit 100 is a synchronization tip holder. The synchronization tip holder 100 includes a coupling capacitor Cl, a comparator 120, a switch 140, a switch 150, and current sources 160 and 170. The synchronization tip holder 100 may also include an optional low pass filter (not shown), the purpose of which will be described after the basic operation of the synchronization tip holder 100 is described. The video signal to be clamped is applied to the input terminal 101 of a coupling capacitor Cl. In the illustrative example, the horizontal synchronization pulses are pulses that are negative, and the excursions that are positive of the active video represent the white areas of the images. The restored direct current or clamped video output signal is provided at the output terminal 102 of the capacitor Cl. The video signal at the output terminal 102 of the capacitor Cl is coupled to an inverting input terminal of the comparator 120. applies a reference potential CLAMP_REF1 to a non-inverting input terminal of the comparator 120. The comparator 120 generates a two-level output signal, which is relatively positive when the amplitude of the video signal is less than CLAMP_REF1, and relatively negative when the amplitude of the video signal is greater than CLAMP REF1.
In unselected mode (USE_ADC_FB = 0), the two-level output of comparator 120 is coupled to switch 150 by switch 140. Switch 150 closes in response to a relatively positive level output of comparator 120. When the switch 150 closes, a constant current from the current source 160 is coupled to the terminal 102 of the capacitor Cl. The current begins to charge the capacitor Cl, such that the direct current voltage level of the signal is increased. As the direct current level of the signal in the terminal 102 increases, the direct current level of the video signal applied to the inverting input of the comparator 120 also increases. When the video signal at the input of the inverting the comparator 120 exceeds the signal CLAMP_REF at the non-inverting input of the comparator 120, the two-level output signal generated by the comparator 120 will become relatively negative. This relatively negative level will cause the switch 150 to open, decoupling, by the same, the current source 160 from the terminal 102. At this time, the current source 170 will start to discharge the capacitor Cl, in such a way that it decreases the Direct current level of the video signal in the terminal 102. The current source 170 is coupled to the terminal 102 and dissipates the current (for example, 1 mA) of the capacitor Cl, tending to lead the terminal 102 to a potential relatively negative The current source 170 ensures that the system does not close at a relatively positive direct current misfire. The first control cycle operates to clamp the direct current level of the signal at terminal 102 to the direct current level of the reference voltage CLAMP_REF1. In the selected mode (USE_ADC_FB = 1), the switch 140 couples the clamping control signal ADC_FB to the switch 150. During the operation of the second control cycle, the switch control signal ADC_FB is used to directly control the switch 150, and the comparator 120 is derived. The clamping control signal ADC_FB is derived by comparing the output of the Analog / Digital converter 310 with a digital word representing a reference level -40 IRÉ. The ADC_FB is also a two-level signal that indicates whether the output level of the converter
Analog / Digital 310 exceeds or not the clamping level -40 IRÉ. Assuming that the instantaneous video signal applied to the 360 comparator contains amplitude levels below -40 IRÉ (representing the "more black-than-black" level of the tip of a synchronization pulse), the two-level output of the ADC_FB comparator of the 360 comparator will be relatively positive. As such, the switch 150 will be closed and a constant current (for example, 25uA) from the current source 160 will begin to charge the capacitor Cl, in such a way that the direct current voltage level of the signal in the terminal is increased. 102. As the direct current level of the video signal in the terminal 102 increases, the video signal applied to the Analog / Digital converter 310 also increases, and the Analog / Digital converter 310 increases in response the level of Direct current of the digital video output signal. When the instantaneous level video signal applied to the comparator 360 does not fall below -40 IRÉ, the two-level output ADC_FB of the comparator 360 will become relatively negative. This relatively negative signal will cause the switch 150 to open, decoupling, by the same, the current source 160 from the terminal 102. At this time, the current source 170 will begin to discharge the capacitor Cl, in such a way as to decrease the Direct voltage voltage level of the signal in terminal 102, and therefore decreases the direct current level of the video signal. This second control cycle operates to hold the minimum amplitude level of the video signal at the -40 IRÉ level. The video signal can be coupled from the output terminal 102 of the capacitor Cl to the comparator 120, through an optional low pass filter (LPF). The low pass filter is used when the input video signal is a composite video signal containing both luminance and chrominance components. When used, the low pass filter may comprise, for example, a series resistor and a bypass capacitor. The 3dB frequency winding point of the low pass filter should be selected to pass the horizontal synch pulses while attenuating the noise and the higher frequency components of the active video signal including the explosion. In addition, the series resistance in the low pass filter should be large enough to prevent the loading of the terminal 102. Referring to Figure 4, an Analog / Digital converter circuit 310 is illustrated together with a comparator 360. it couples an analog video signal A_CLAMPED received from a clamping circuit (for example, the clamp 100 by the switch 300) to an Analog / Digital converter 310A. The Analog / Digital converter 310A converts the analog video signal A_CLAMPED to a digital video signal D_CLAMPED comprising a series of digital words corresponding to respective samples of the analog video signal A_CLAMPED at a sampling rate determined by the frequency of a signal of CLOCK timing. In the exemplary mode, an 8-bit Analog / Digital converter is used. The digital signal D_CLAMPED is coupled to a digital signal processor 320 (shown in Figure 1). The ADC FB holding control signal is derived by coupling the digital video signal D_CLAMPED to the comparator 360. A chrominance stepping filter 310B can be inserted between the Analog / Digital converter 310A and the comparator 360 for the reasons given. explain later. The chrominance stepping filter 310B can be used to separate the chrominance components when the digital video signal D_CLAMPED contains both luminance and chrominance components. The comparator 410C compares the digital video signal D_CLAMPED with a signal representative of the -40 IRÉ level, as described above. Those skilled in the art will appreciate that the optional chrominance step 310B and comparator 360, described above, can be implemented by a variety of circuits, for example discrete logic, state machines, digital signal processors (DSPs), and so on. The Analog / Digital converter circuit 310 includes a resistance ladder network 310G comprising several resistors connected in series, although the only resistors shown are higher resistors Rl, R8, R24 and R256 (connected to V +) and lower (connected to ground) ). The upper and lower conversion amplitude of the Analog / Digital converter 310A is adjusted by voltage reference leads in the upper and lower resistors. The remaining resistors determine the discrete reference voltage steps used by the Analog / Digital converter 310A to convert the analog video signal A_CLAMPED into the digital video signal D_CLAMPED. The signal CLAMP_REF is derived from the voltage level in the ladder resistance R8 by means of a separating amplifier 310D. This voltage corresponds to the appropriate reference level for the synchronization tip of the video signal A_CLAMPED. The CLAMP_REF signal can be provided to each of the clamping circuits to replace the reference signals CLAMP_REF1, CLAMP_REF2 ... CLAMP_REFN. By using CLAMP_REF as the unselected mode reference level, the unselected input video signals CVl and CV2 are clamped through CVN at a brightness level directly related to the operating range of the analog / digital converter 310A . As such, when an unselected video signal is selected for video processing, there will be variations of undesirable brightness of the small image (if there is any). When an input video signal is not selected for processing, the inventive clamping arrangement holds the unselected video signal at a direct current voltage level. When the video input not selected for processing is subsequently selected, the inventive clamping arrangement will be able to change from the unselected mode to the selected mode, while keeping the video signal clamped within the direct current level limits of the channel. image-in-image processing. The transition response is quite fast because the unselected video signal was previously subjected to a direct current level close to the level required for the selected video signal. As explained above, this approach can be improved by using an inactive mode clamping level derived from the ladder network of the Analog / Digital converter in the selected channel. Referring to Figure 3, a video signal processing system similar to the system of Figure 1 is shown. The television system of Figure 3 includes N video inputs, although only three, 101, 201 and 301 of the N entries. The first composite video input signal CVl is held by CLAMP1, which includes a capacitor Cl and (not shown) a comparator 120, a switch 140, a switch 150, and current sources 160 and 170. A second input signal CV2 composite video is held by CLAMP2, which includes a capacitor C2. The third CV3 composite video input signal is held by CLAMP3, which includes a capacitor C3. Unlike the video signal processing system of Figure 1, the system of Figure 3 allows selectable feedback from the circuit breaker to the clamping circuits either from the main Analog / Digital converter circuit 410 or from the converter circuit Analog / Image-in-picture digital 310. The output signals of the two analog / digital converter circuits 310 and 410 are coupled to a feedback switch and comparator circuit 900, which is responsive to the controller 350. The feedback switch and circuit comparator 900 includes a first comparator for comparing the output of the main analog / digital converter with a digital word representing -40 IRÉ and a second comparator for comparing the output of the analog / digital image-in-picture converter to a digital word representing -40 I WILL GO. Each of the comparator circuits operates in the manner described above with respect to the comparator 360, and each comparator produces a respective output signal. The feedback switch and comparator circuit 900 also includes a switching network that controllably couples the output of any comparator to any of the three CLAMP1-CLAMP3 clamping circuits as clamping switch control signals ADC_FB1, ADC_FB2 or ADC_FB3, respectively . In addition, the feedback switch and comparator network 900 provides the three respective clamp selection signals USE FB ADC, USE_ADC_FB2, and USE_ADC_FB3 in response to controller 350. The video signal processing system of the
Figure 3 allows the subjection of the main input and image-in-picture video signals at levels determined by the respective main analog-to-digital and image-in-picture converting circuits. The present invention has been described in terms of conventional video signals, including horizontal synchronization components, however, it should be appreciated that this can be applied to any signals having, for example, pulse intervals, the amplitude of which carries some relation to the direct current reference value of the signal. It will be obvious to those skilled in the art that, although the present invention has been described in terms of specific examples, modifications and changes can be made to the embodiments described without departing from the essence of the present invention. For example, although the present invention has been described in terms of certain types of video signals, such as composite video signals may also be applied when processing other types of video signals, such as component video signals. In addition, although the present invention has been described with reference to a mode in which a digital processing channel is used, it can also be applied when an analog signal processing channel is used. It should be understood, therefore, that the appended claims are intended to cover all modifications that naturally flow from the foregoing description and examples.