[go: up one dir, main page]
More Web Proxy on the site http://driver.im/

MXPA96002205A - Liquid crystal screen with common connection lines transferred by pixel electrodes and an insulating photo-image former layer between the - Google Patents

Liquid crystal screen with common connection lines transferred by pixel electrodes and an insulating photo-image former layer between the

Info

Publication number
MXPA96002205A
MXPA96002205A MXPA/A/1996/002205A MX9602205A MXPA96002205A MX PA96002205 A MXPA96002205 A MX PA96002205A MX 9602205 A MX9602205 A MX 9602205A MX PA96002205 A MXPA96002205 A MX PA96002205A
Authority
MX
Mexico
Prior art keywords
layer
liquid crystal
pixel
crystal display
insulating layer
Prior art date
Application number
MXPA/A/1996/002205A
Other languages
Spanish (es)
Other versions
MX9602205A (en
Inventor
Den Boer Willem
Zz Zhong John
Gu Tieer
Original Assignee
Ois Optical Imaging Systems Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Ois Optical Imaging Systems Inc filed Critical Ois Optical Imaging Systems Inc
Publication of MXPA96002205A publication Critical patent/MXPA96002205A/en
Publication of MX9602205A publication Critical patent/MX9602205A/en

Links

Abstract

The present invention relates to an active matrix liquid crystal display (AMLCD) having a high pixel aperture ratio. The screen has an increased pixel aperture ratio, because the pixel electrodes are formed on the insulating layer to overlap portions of the array direction lines. Both the manufacturing capacity and capacitive crosstalk of the TFT-based device are improved by the use of an insulating photoformer layer of images between the pixel electrodes and the direction lines. According to certain other embodiments, the insulating layer can be BCB (either image photoformer or not) and / or have a dielectric constant of less than about 3.

Description

LIQUID CRYSTAL SCREEN WITH COMMON CONNECTION LINES TRANSFERRED BY PIXEL ELECTRODES AND AN INSULATING LAYER PHOTO- IMAGE FORMER BETWEEN THEM This invention relates to a liquid crystal display (LCD) having an increased pixel aperture ratio. More particularly, this invention relates to a liquid crystal display that includes a TFT arrangement, in which an insulating layer having a plurality of contact paths or openings disposed therein, is located between the address lines and the pixel electrodes, such that the pixel electrodes are allowed to overlap the column and row direction lines without exposing the system to capacitive crosstalk. In certain embodiments, the dielectric constant of the insulating layer is less than about 3.0 to reduce crosstalk. In certain embodiments, the layer is image shaper.
BACKGROUND OF THE INVENTION Electronic matrix arrangements find considerable application in ray image detectors X and active matrix liquid crystal displays (the AMLCD). Such AMLCDs generally include X and Y (or row and column) direction lines, which are horizontally and vertically separated and intersect from one angle to another angle whereby they form a plurality of crossing points. Associated with each cross-linking point, there is an element (for example, a pixel) that is to be targeted. These elements are in many cases liquid crystal display pixels or alternatively, the memory cells or pixels of an electronically adjustable memory arrangement or an X-ray detector arrangement. Typically, a switching or isolation device such as a diode or A thin film transistor (TFT) is associated with each array element or pixel. The isolation devices allow the individual pixels to be selectively addressed by the application of suitable potentials between respective pairs of X and Y direction lines. In this way, the TFTs act as switching elements to energize or address in any other form electrodes. corresponding pixels. Amorphous silicon (a-Si) TFTs have found wide use for isolation devices in liquid crystal display (LCD) arrangements. Structurally, the TFTs generally include a substantially coplanar source and drain electrodes, a thin film semiconductor material (eg, a-Si) placed between the source and the drain electrodes and a gate electrode in proximity to the semiconductor, but isolated electrically from it by a gate insulator. The flow of current through the TFT between the source and the drain is controlled by the application of the voltage to the gate electrode. The voltage for the gate electrode produces an electric field, which accumulates a charged region near the interface of the semiconductor-gate isolator. This charged region forms a channel that carries the current in the semiconductor through which the current is transported. In this way, by controlling the voltage to the gate and drain electrodes, the pixels of an AMLCD can be I switched to on and off in a known manner. Typically, the pixel aperture ratios (i.e., pixel apertures) in the non-overlapping AMLCDs are only about 50% or less. As a result, either the luminance of the screen is limited or the power consumption of the backlight is excessive, thus avoiding or limiting use in certain applications. Thus, it is known in the art that it is advantageous to increase the pixel aperture ratio or the pixel aperture size of the LCDs to as high a value as possible to avoid these problems. The higher pixel aperture ratio (or pixel aperture size) of a screen, for example, the transmission of exhibition is greater. In this way, by increasing the pixel aperture ratio of a screen, the transmission can be increased using the same backlight energy, or alternatively, the backlight energy consumption, can be reduced while maintaining the same luminance of the screen. It is known to overlap pixel electrodes in address lines to increase the pixel aperture ratio. For example, "High-Aperture TFT Array Structures" by K. Suzuki presents an LCD that has a flat ITO shield configuration that has a pixel aperture ratio of 40% and pixel electrodes which overlap the common signal connection lines. An ITO pattern in Suzuki located between the pixel electrodes and the signal lines works as a plane to ground in such a way that it reduces the connection capacitance between the signal lines and the pixel electrode. Unfortunately, it is not always advantageous to have a shielding electrode placed along the length of the signal lines as in Suzuki, due to production and cost considerations. The arrangement of the shielding layer as described by Suzuki requires extra processing steps and thus presents production problems. Accordingly, there is a need for the technique for an LCD with an increased pixel aperture ratio, which does not require a flat ITO shield structure to be placed between the signal lines and the pixel electrode. It is ancient and well known to manufacture TFT arrangements for LCDs in which the address lines and the overlapping pixel electrodes are insulated from each other by an insulating layer. For example, see U.S. Patent Nos. 5,055,899; 5,182,620; 5,414,547; 5,426,523; 5,446,562; 5,453,857; and 5,457,553. U.S. Patent 5,182,620 discloses an AMLCD that includes pixel electrodes, which at least partially overlap the direction lines and the additional capacitor lines, so that a larger numerical aperture for the screen is achieved. The pixel electrodes are insulated from the direction lines, which overlap by an insulation layer formed of silicon oxide or silicon nitride. Unfortunately, the method of manufacturing this screen as well as the resulting structure is less advantageous, because: (i) chemical vapor deposition (CVD) is required to deposit the silicon oxide or silicon nitride of the insulating film; and (ii) the silicon oxide and the silicon nitride are not image-forming (ie, the orifices or contact paths must be formed in such insulating layers by means of chemical etching). As a result of these two problems, the manufacturing process is expensive and requires more stages than would be otherwise advantageous. For example, to etch the contact holes in an insulating step, an additional photoresist coating step is required and the user must be related about the underlying layers of the insulating layer during etching. With respect to CVD, this is a deposit process that requires expensive equipment. U.S. Patent 5,453,857 discloses an AMLCD having a TFT array with pixel electrodes formed in an overlapping relationship with source signal lines through a thin insulating film. The thin insulating film formed between the signal lines and the pixel electrodes are made of either SiN ?, Si02, taO? or Al203. Unfortunately, the method for manufacturing the resulting layout and screen of the '857 patent suffers from the same problems discussed in the above with respect to the' 620 patent. None of the possible insulating layer materials are photo-imagers and etching is required. U.S. Patent No. 5,055,899 discloses a TFT arrangement that includes an insulating film placed between the address lines and the pixel electrodes. Again, etching is required to form the lines in the insulating film. This is undesirable. U.S. Patent No. 5,426,523 discloses an LCD that includes overlapping pixel electrodes and common source connection lines, with an insulating silicon oxide film placed therebetween. Silicon oxide is not an image-forming agent and thus requires a longer and more difficult manufacturing process for the TFT arrangement and the resulting AMLCD. It is apparent from the foregoing, that there is a need for the technique for an improved TFT array and / or resulting LCD that has an increased pixel aperture ratio and little capacitive crosstalk and a more efficient manufacturing method. The manufacturing method, which is improved in relation to the prior art, should include forming an insulating photo-forming layer between the pixel electrodes and the overlapping common connection lines and the ways in which by means of the photo - Image formation on the contrary to the resistant coating, exposure and development and etching by wet or dry attack. It is a purpose of this invention to meet the needs described above in the art, as well as other needs which will become apparent to the skilled artisan from the following description of this invention.
BRIEF DESCRIPTION OF THE INVENTION Generally speaking, this invention meets the needs described above in the art, by providing a high-aperture LCD, comprising: first and second substrates; a liquid crystal layer sandwiched between the first and second substrates; a thin film transistor (TFT) array placed on the first substrate, the TFT array includes a plurality of address lines connected to the TFT; an array of substantially transparent pixel electrodes, placed on the first substrate, a plurality of pixel electrodes in the array of pixel electrodes that overlap at least one of the direction lines, thereby increasing the pixel aperture ratio of the LCD; an image-forming isolator layer positioned on the first substrate between the address lines and the pixel electrodes, at least in the overlapping areas and areas adjacent to the source electrodes of the TFT; and the photo-image-forming insulating layer having a first group of contact paths defined therein by the photo-formation, in which the pixel electrodes are in electrical communication with the corresponding TFT source electrodes, through of the contact paths of the first group defined in the insulating layer. According to certain preferred embodiments, the insulating photo-forming layer includes one of BCB and 2-ethoxyethyl acetate. This invention also meets the needs described in the art in the foregoing by providing an LCD comprising: a liquid crystal layer; a substantially transparent substrate adjacent to the liquid crystal layer; an arrangement of the TFTs placed on the substrate, the TFTs connected to the address lines and acting as switching elements to energize the corresponding pixel electrodes; a substantially transparent planarization layer placed on the transistor array, the planarization layer is located between the pixel electrodes and the address lines, and wherein the planarization layer includes BCB and has a dielectric constant of less than about 3.0. This invention still further meets the needs described above, in the art, by providing a method for manufacturing a TFT-based semiconductor arrangement, the method comprising the steps of: providing a substantially transparent first substrate; forming a corresponding TFT array and address lines on the substrate; deposit an insulating, photo-forming layer, organic on both of the TFT arrangement and the corresponding address lines; photographing the image of the insulating layer to form a first arrangement of contact holes therein; and forming a disposition of electrode members in the first substrate on the isolating photo-forming layers, in such a way that the electrode members in the arrangement are in communication with the corresponding TFTs by means of the first contact arrangement.
Now this invention will be described with reference to certain of its modalities as illustrated in the following drawings.
BRIEF DESCRIPTION OF THE DRAWINGS Figure 1 is a top view of an AMLCD according to this invention, this figure illustrates overlapping pixel electrodes, surrounding row and column direction lines, along their respective lengths throughout the pixel area of the screen , to increase the pixel aperture ratio of the screen. Figure 2 is a top view of the direction lines of the column (or drain) and corresponding to the drain electrodes of Figure 1, this figure also illustrates the TFT source electrodes, placed adjacent to the drain electrodes for define the TFT channels. Figure 3 is a top view of the pixel electrodes of Figure 1, except for their extensions. Figure 4 is a cross-sectional, side elevation view of the transistors of the linear thin film (TFT) of Figures 1-2. Figure 5 is a cross-sectional, side elevation view of the liquid crystal display of Figure 1.
Figure 6 is a top and bottom view of the optimal black matrix to be placed on a substrate of the LCD of Figures 1-5, the black matrix will be placed on the substrate that does not have the TFT arrangement placed about him . Figure 7 is a cross-sectional, side view of a portion of the LCD of Figures 1-6, this figure illustrates the pixel electrodes overlapping the column direction lines. Figures 8-11 are cross-sectional views, in side elevation illustrating how a TFT in an arrangement in accordance with this invention is manufactured.
DETAILED DESCRIPTION OF CERTAIN MODALITIES OF THIS INVENTION Now with reference more particularly to the accompanying drawings, in which like reference numbers indicate similar parts in all the various views. Figure 1 is a plan view of four pixels in an active matrix liquid crystal display (AMLCD) 2 arrangement according to an embodiment of this invention. This portion of the screen includes pixel electrodes 3, drain direction lines 5, gate address lines 7, an array of four thin film transistors 9 (TFT), and auxiliary storage capacitors 11 associated with each pixel. Each storage capacitor 11 is defined on one side by a gate line 7 and on the other hand by an independent storage capacitor electrode 12. The storage capacitor electrodes 12 are formed together with the drain electrodes 13. As shown, the longitudinally extending edges of each pixel electrode 3 overlap the drainage lines 5 and the gate lines 7, respectively, along their edges to increase the pixel aperture ratio (or size of the pixel). pixel aperture) of the LCD. In the areas of overlap 18 between the pixel electrodes 3 and the common connection direction or lines 5, 7, a pixel-line capacitor (PL) is defined by an electrode 3 on one side and the address line overlapped on the other side. other. The dielectric material placed between the electrodes of these capacitors PL is the insulating layer 33 (see Figures 4 and 7). The parasitic capacitance CpL of these capacitors is defined by the equation: 'PL £ where "d" is the thickness of layer 33, e is the dielectric constant of layer 33, eQ is the constant 8.85 x 10-14 F / cm (permissiveness in vacuum) and "A" is the area of capacitor PL in overlap areas 18. The effects of the capacitance can also be taken into consideration in a known way. See Diagram 1 below for certain modalities. Also, according to other certain embodiments CpL is less than, or equal to about 0.01 pF for a screen with a pixel spacing of approximately 150 μm. When the pixel spacing CpL is smaller, it must be calculated at a lower value as well, because the overlap areas 18 are smaller. Additionally, the pixel aperture ratio of an LCD decreases as the pixel spacing decreases as is known in the art. The pixel spacing of the AMLCD 2 may be from about 40 to 5,000 μm according to certain embodiments of this invention. Pixel spacing, as is known in the art, is the distance between adjacent pixel centers in the array. Figure 2 is a top view of the drainage direction lines 5 of the AMLCD 2 showing how the extensions of the steering lines 5 form drainage electrodes 13 of the TFT 9. Each TFT 9 in the arrangement of the AMLCD 2 it includes the source electrode 15, the drain electrode 13 and the gate electrode 17. The gate electrode 17 of each TFT 9 is formed by the corresponding gate address line 7, adjacent to the TFT according to certain modalities. According to other embodiments, the gate electrode 17 may be formed by a branch extending substantially perpendicular to the gate line. Figure 3 is a top view illustrating the pixel electrodes 3 (absent their extension portions 38) of the AMLCD 2 arranged in an array form. Figures 2 - 3 are provided in such a way that Figure 1 can be interpreted more easily. Figure 4 is a cross-sectional view, of a single thin film transistor (TFT) 9 in the TFT array of the AMLCD 2, with each TFT 9 in the arrangement which is substantially the same according to the preferred embodiments. Each linear TFT 9 has a channel length "L" defined by the space 27 between the source electrode 15 and the drain electrode 13. The source electrode 15 is connected to the pixel electrode 3 via the path or contact hole 35 to allow the TFT 9 to act as a switching element and selectively energize a corresponding pixel in AMLCD 2, to provide image data to an observer. An arrangement of the TFTs 9 was provided as illustrated in Figure 1 for the AMLCD 2. Each TFT structure 9 substantially includes a transparent substrate 19 (eg, made of glass), a metal gate electrode 17, an insulating layer of gate or film 21, a semiconductor layer 23 (eg, intrinsic amorphous silicon), a contaminated semiconductor contact layer 25, the drain electrode 13, the source electrode 15, substantially the transparent insulation layer 33 and an electrode 3 corresponding pixel. The TFT channel 27 of length "L" is defined between the source 15 and the drain 13. As shown in Figure 4, the drain electrode 13 is made of the drainage metal layer 29 (e.g., Mo) the which is deposited on the substrate 19 on the upper part of the adulterated contact layer 25. The contact film or layer 25 can be, for example, amorphous silicon contaminated with an impurity such as phosphorus. (ie, n + a- Si) and is sandwiched between the semiconductor layer 23 and the drainage metal layer 29. The source electrode 15 includes the contaminated semiconductor contact layer 25 and the source metal layer 31. The metal layers 29 and 31 may be of the same metal and deposited and patterned together in accordance with certain embodiments of this invention. Alternatively, the layer 29 can be deposited and form a pattern separately from the layer 31, such that the drainage metal layer is made of a metal (e.g., Mo) and the source metal layer 31 is of another ( for example, Cr). The substantially transparent insulating layer 33 has a dielectric constant less than about 5.0, which is deposited as a sheet on the substrate 19 to cover the TFT 9 and the address lines 5 and 7. The layer 33 is formed of an image-forming material such as Fuji ClearMR or a type of BCB image-shaper. The insulating layer 33 is continuous in the observation area of the screen, except for the contact paths or holes 35 and 36 formed therein to allow the pixel electrodes 3 to make contact with the corresponding TFT source electrodes and the capacitor electrodes storage, respectively (ie, each pixel includes two paths (35 and 36) in the insulating layer 33 - one for the source electrode and the other for the storage capacitor). The layer 33 has a dielectric constant less than or equal to about 5.0 according to certain embodiments of this invention. In certain preferred embodiments, the layer 33 has a dielectric constant of about 2.7 and is made of a photo-forming type of benzocyclobutene (BCB), an organic material available from Dow Chemical, for the purpose of reducing capacitive crosstalk (or capacitive connection) between the pixel electrodes 3 and the direction lines in the overlapping areas 18. The layer 33 has a low dielectric constant and / or a relatively large thickness for the specific purpose of reducing CpL in the overlapping areas 18. Note that the BCB may be of the type that does not form photoimages according to certain modalities, it still reduces crosstalk. Alternatively, the layer 33 may be of an image-forming material known as Fuji Clear ™, which is an organic mixture that includes 2-ethoxyethyl acetate (55-70%), a copolymer derived from methacrylate (10-20%). ), and polyfunctional acrylate (10-20%). After the deposition of the insulation layer 33 on the substrate 19 on top of the TFT 9 and the steering lines 5 and 7, the tracks 35 and 36 are formed in the insulation layer 33 by means of the photo image formation The layer 33 acts as a negative protective layer in such a way that the exposed areas remain on the substrate and the areas of the layer 33 without exposing to the UV during the imaging are removed during the development. After the formation of the tracks 35 and 36, substantially transparent pixel electrodes 3 (made of indium tin oxide or ITO) are deposited and forming a pattern on the layer 33 on the substrate 19, in such a way that the electrodes 3 of pixel make contact with the corresponding source metal layers 31 of the corresponding TFTs 9, through the tracks 35 as illustrated in Figure 4. The auxiliary tracks 36 (see Figure 1) are formed in layer 33 at the same time that the channels 35, in such a way that the pixel electrodes 3 can make contact with the storage capacitor electrodes 12 by means of the pixel electrode extensions 38. The peripheral front areas and seal areas are also removed by photo-imaging. The insulation layer 33 is deposited on the substrate 19, on the address lines, the storage capacitors and the TFTs at a thickness "d" of at least about 0.5 μm in the overlapping areas 18. In the preferred modalities, the thickness "d" of the insulating layer 33 is approximately 1 to 2.5 μ. Another advantage of the layer 33 is that the inclinations of the liquid crystal layer induced at the edges of the pixel electrode 3 by the topography of the TFT 9, the storage capacitors and the direction lines are substantially eliminated by the planarization (it is say, few, if any, hills and valleys are present on the upper surface of layer 33). In this way, the thickness of the LC layer is substantially maintained and exhibits functionality that is improved because the electrodes 3 are substantially flat due to substantial planarization of the surface of the layer 33 adjacent the pixel electrodes 3. Due to the low dielectric constant e and / or relatively high thickness "d" of layer 33, capacitance crosstalk problems of the prior art resulting from excessively high Cp values are substantially reduced in areas 18, where the electrodes 3 of pixel overlap lines 5 and / or 7 of direction. Because the layer 33 is positioned between the pixel electrodes 3 and the overlapping address lines, the capacitance crosstalk problems of the prior art are substantially reduced or eliminated and the increased pixel apertures can be achieved without sacrificing the operation of the screen (pixel isolation). The pixel aperture sizes or the pixel aperture ratio of the AMLCD 2 is at least about 65% (preferably about 68% to 80%) according to certain embodiments of this invention, when the pixel separation is of approximately 150 μm. This, of course, will vary depending on the pixel spacing of the screen (pixel spacings of approximately 40-500 μm can be used). The pixel electrodes 3 overlap the direction lines 5 and 7 along their edges as shown in Figure 1 by an amount of up to about 3 μm. In certain preferred embodiments of this invention, the overlap 18 of the electrodes 3 on the edges of the direction lines 5 and 7 is designed to be about 2 to 3 μm, with the final result after etching over etching which is of at least 0.5 μm. According to certain other embodiments of this invention, the amount of overlap can be designed to be approximately 2-3 μm, with the resulting post-processing overlap that is approximately 0 to 2 μm. The amount of overlap can be adjusted according to different LCD applications and pixel separation sizes as will be appreciated by those skilled in the art. In certain situations, after etching and processing, the pixel electrodes 3 can not overlap the address lines at all according to certain embodiments of this invention, although some overlap is preferred. When no overlap occurs, the parasitic capacitance CpL between the address lines and the adjacent pixel electrode 3, is still reduced or minimized due to the insulating layer 33. Now with reference to Figures 4-5 and 8-11, it will be described how the AMLCD 2 including the arrangement of the TFT structures and the corresponding address lines, is made in accordance with an embodiment of this invention. First, substrate 19 is substantially transparent. Next, a layer or sheet of metal or gate (which results in the electrodes 17 and gate lines 7) is deposited on the upper surface (the surface that will be closest to the LC layer) of the substrate 19 to a thickness of about 1,000 -5,000 Á, preferably a thickness of about 2,500 Á. The gate metal sheet is deposited by means of cathodic electrodeposition or vapor deposition. The gate metal may be of tantalum (Ta) according to certain embodiments of this invention. The insulating substrate 19 can be glass, quartz, sapphire or similar. The structure, including the substrate 19 and the deposited gate metal, are then formed in a pattern by photolithography for the gate electrode 17 and the configuration of the desired gate direction line 7. The upper surface of the gate metal is exposed in a window, where the photoresistor has not been retained. The gate metal layer (eg, Ta) is then etched by dry etching (preferably using etching by reactive ionic chemical) to form a pattern of the gate metal layer according to the pattern of the retained photoresistor. In doing so, the structure is mounted on a well-known ionic etching, reagent (RIE) etching apparatus, which is then purged and evacuated according to RIE chemical procedures and mordants. This etching of the gate metal layer is preferably carried out until the gate metal is removed in the central areas of the windows and then allowed to proceed for an additional time (for example, 20 a 40 seconds) of chemical etching to ensure that the gate metal is completely removed from inside the windows. The result is the gate direction lines 7 (and gate electrodes 17) that are left on the substrate 19. After the gate address lines 7 are deposited and form a pattern on top of the substrate 19 in As described above, the insulating or dielectric gate layer 21 is deposited on substantially all of the substrate 19 preferably by plasma chemical vapor deposition (CVD) or some other known process that produces a high dielectric integrity. The resulting structure is shown in Figure 8. The gate insulator layer 21 is preferably silicon nitride (Si3N4), but it can also be silicon dioxide or other known dielectric materials. The silicon nitride has a dielectric constant of about 6.4. The insulating gate layer 21 is deposited to a thickness from about 2,000-3,000 Á (preferably either approximately 2,000 Á or 3,000 Á) according to certain modalities. It is noted that after the anodization (which is optional), the gate Tail 17 layer, which was deposited as the gate electrode and the gate line layer (when originally it was approximately 2,500 A thick) it is approximately 1,800 Á thick and a newly created TaO layer is approximately 1,600 Á. The anodization is carried out after the pattern formation of the gate line and before further processing. In this way, the insulating gate layer 21 on the lines 7 and gate electrodes 17 is made of both the TaO layer and the silicon nitride layer created by anodization. Other metals from which the gate electrode 17 and the address line layer 7 can be made include Cr, Al, titanium, tungsten, copper and combinations thereof. Then, after the gate insulation layer 21 has been deposited (Figure 8), the semiconductor layer 23 (eg, intrinsic a-Si) is deposited on the top of the gate insulation layer 21 to a thickness of approximately 2,000 Á. The semiconductor layer 23 may be from about 1,000 A to 4,000 A thick in certain embodiments of this invention. Then, the contaminated amorphous silicon contact layer 25 (typically contaminated with phosphorus, is n +) is deposited on the intrinsic a-Si layer in a known manner at a thickness, for example, of about 500 A. The contaminated contact layer 25 can be from about 200 A to 1,000 A thick according to certain embodiments of this invention. The result is the structure of Figure 9. The gate insulator layer 21, the semiconductor layer 23 and the semiconductor contact layer 25, can be deposited on the substrate 19 in the same deposit chamber without breaking the vacuum according to certain embodiments of this invention. When this is done, the plasma discharge in the reservoir chamber stops after completing the deposit of a particular layer (eg, the insulation layer 21) until the gas composition suitable for the deposition of the next layer ( for example, the semiconductor layer 23) is established. Subsequently, the plasma discharge is re-established to the deposit of the next layer (e.g., the semiconductor layer 23). Alternatively, the layers 21, 23 and 25 can be deposited in different chambers by any known method.
After the formation of the structure of Figure 9, the island or TFT area can be formed by etching, for example, in such a way that the TFT metal layers can be deposited thereon. Optionally, one of the TFT metal source / drain layers can be deposited before forming the TFT island. According to the preferred embodiments, after the formation of the TFT island of the structure of Figure 9, a source / drainage metal layer or sheet (which results in the drainage metal layer 29 and the drainage layer 31). metal source) is deposited on the substrate 19 on top of the semiconductor layer 23 and the contact layer 25. This source / drain metal layer can be chromium (Cr) or molybdenum (Mo) according to certain embodiments of this invention. When it is chromium, the layer is deposited to a thickness of approximately 500-2,000 A, preferably approximately 1,000 A, according to certain modalities. When it is molybdenum, the layer is deposited to a thickness of approximately 2,000 to 7,000 Á, preferably of approximately 5,000 Á. The deposited source drain metal layer sheet is then formed in a pattern (masked and etched) to form the source, drain, and storage capacitor electrodes. After forming the pattern of the source and drain TFT electrodes, the result is the TFT structure of Figure 10. Alternatively, a first metal layer can be deposited and formed in a pattern to form the drain electrode portion 29 and the storage capacitor electrode 12 and a second metal layer can be deposited and form a pattern to form the source electrode portion 31. In this way, for example, the source metal layer 31 may be chromium (Cr), while the drainage metal 29 and the storage capacitor electrode layer is Mo according to certain embodiments of this invention. Other metals, which can be used for the source and drain metals include titanium, Al, tungsten, tantalum, copper or the like. After forming the pattern of portions 29 and 31 of drainage and source, the contact layer 25 is etched by etching in the area of the channel 27 and inevitably a bit of the semiconductor layer 23 is etched together with it. The result is TFT 9 with channel 27 as shown in Figures 4 and 10. The substantially transparent polymer insulating layer 33 is then deposited substantially on substrate 19 by means of rotating coating according to certain embodiments of this invention. . The layer 33 can be either BCB photo-imager or Fuji ClearMR according to certain embodiments. The insulating layer 33 fills the grooves or recesses generated on the formation of the TFT 9 and flattens the surface above the substrate 19 by at least about 60% according to certain embodiments. The result is the structure of Figure 11. The insulating layer photo-imager 33 acts as a negative protective layer according to certain embodiments of this invention, such that no additional photoresistor is necessary to form the tracks 35 and 36 in layer 33. To form the pathways, layer 33 is irradiated by ultraviolet (UV) rays (e.g., 365 nm i-rays), with UV-irradiated areas of layer 33 so that they remain and are not unexposed areas. or without irradiating the layer 33 to be removed during development. A mask can be used. In this way, the areas of the negative protective layer 33 corresponding to the tracks 35 and 36 are not exposed to UV radiation, although the rest of the layer 33 through the substrate is exposed to UV light. After exposure of layer 33 (except in the pathway or contact hole areas), layer 33 is developed using a known developer solution at a known concentration. In the development stage, the areas of layer 33 corresponding to tracks 35 and 36 are eliminated (i.e., dissolved) to form the tracks of the insulating layer. After development, the resist layer 33 is cured or subjected to post-cooking (eg, about 240 degrees C for about one hour) to remove the solvent, such that the layer 33 with the pathways in it is resinated. In this way, chemical etching or wet etching is not necessary to form the tracks in the layer 33. According to alternative embodiments, the layer 33 can be a positive protective layer on the contrary to a negative protective layer. The paths or openings 35 are formed in the insulating layer 33 of the top of (or adjacent to) each source metal electrode 31, to allow the pixel electrodes 3 to electrically contact the corresponding source electrodes 15 by means of the tracks_35. Layer 33 remains through the remainder of the substrate or arrangement, except for the capacitor storage paths and certain edge areas, where the contacts must be made or made by gluing with cement. After the tracks 35 and 36 are formed in the layer 33, a substantially transparent conductive layer (e.g., ITO), which results in the pixel electrodes 3 being deposited and forming a pattern (photo-masked and etched by etching) on the substrate 19 on top of the layer 33. After pattern formation (eg, masking and etching) of this substantially transparent conductive layer, the electrodes 3 of pixel are left as shown in Figures 1 and 4. As a result of tracks 35 and 36 formed in layer 33, each pixel electrode 3 contacts a TFT source electrode 31 as shown in Figure 4 and an electrode 12 storage capacitor as shown in Figure 1. The result is the active plate of Figures 1 and 4 including an arrangement of the TFTs. The pixel electrode layer (when made of ITO) is deposited at a thickness of about 1,200 to 3,000 Á (preferably about 1,400 Á) in accordance with certain embodiments of this invention. Other known materials can be used as the pixel electrode layer 3. After formation of the active plate, the liquid crystal layer 45 is placed and sealed between the active plate and the passive plate as shown in Figure 5, the passive plate including the substrate 51, the polarizer 53, the electrode 49 , and the orientation film 47. As shown in Figure 1, the pixel electrodes 3 are formed in a pattern to a size such that they overlap both of the drainage direction lines 5 and the gate direction lines 7 along their edges. , to result in an increased pixel aperture ratio for the AMLCD 2. The crosstalk problems of the prior art are substantially eliminated due to the presence of the layer 33 in the overlap areas 18 between the electrodes 3 and the lines of direction. Alternatively, the pixel electrodes may only overlap a group of address lines (e.g., row lines) according to certain modalities. Figure 5 is a cross-sectional view, in lateral elevation of the AMLCD 2 (absent the TFT, the direction lines and the black matrix). As shown, the rotated nematic screen includes from the front back toward the observer, the rear polarizer 41, the substantially transparent substrate 19, the pixel electrodes 3, the rear orientation film 43, the liquid crystal layer 45, the front facing film 47, common electrode 49, substrate 51 substantially transparent, front and finally front polarizer 53. The polarizers 41 and 53 may be arranged in such a way that their transmission axes are either parallel or perpendicular to each other, to define a normally black or normally white AMLCD, respectively. Optionally, retarders can also be provided. Typically, a backlight is provided behind the polarizer 41, so that the light emitted from it, first goes through the polarizer 41, then through the liquid crystal layer 45 and finally out of the front polarizer 53 towards the observer . The pixel electrodes 3 work selectively together with the common electrode 49 to selectively apply voltages through the liquid crystal layer 45, to cause an image (preferably color, according to certain embodiments) to be observed from the front of the liquid crystal. the screen. Figure 6 illustrates an optional black matrix pattern (BM) that is placed on the front substrate 51 for the purpose of overlapping the address lines 5 and 7 and the TFT channels 27. When the ITO of the pixel electrodes 3 overlaps the direction lines, the direction lines by themselves, are effectively the light that blocks the black matrix in the interpixel areas. However, the low-reflectance black matrix 55 with a larger than normal aperture is still useful in the upper (or passive) plate to reduce the specular reflectance and to avoid the incidence of ambient light on the TFT channels. Thus, the pixel opening ratio of the screen can be made larger, because the pixel electrode area is larger and the overlap between the pixel electrodes on the active plate and the black matrix 55 on the passive plate can be reduced. The black matrix structure 55 includes vertically extending regions 56 and horizontally extending regions 57. The regions 56 are aligned with the drainage lines 5, while the regions 57 are aligned with the gate lines 7, to prevent ambient light from entering the screen. Additionally, the black matrix 55 includes portions 58 that cover the channel, which are aligned with the channels 27 TFT for the purpose of preventing ambient light from reaching the semiconductor layer 23 of amorphous silicon through the channels. As is commonly known in the art, pixel apertures 65 of the screen are substantially defined by (i.e., joined by) black matrix regions 56 and 57. Figure 7 is a cross-sectional, side elevation view of a portion of the AMLCD 2. As shown, the central pixel electrode 3 illustrated in Figure 7 overlaps both of the column direction lines 5 or drainage by a "w" amount, whereby the pixel electrode size increases in relation to that of many screens of the prior art. The electrodes 3 are separated from the direction lines by a distance "d". Also, the portions 56 of the black matrix align with the direction line 5 such that the pixel opening or hole for the central electrode 3 is defined in part by the distance between the black matrix members 56. The black matrix portions 56 and the direction lines 5 are both arranged in such a way that their central axes correspond to the spaces between the pixel electrodes 3 according to certain embodiments of this invention. The presence of layer 33 substantially reduces the parasitic capacitance of the capacitor created between the pixel electrodes 3 and the address lines 5 in the overlapping areas 18 as set forth above. Now this invention will be described with respect to certain examples set forth in Table 1 below.
TABLE 1 The values set forth in the above in Table 1 are for a presentation in which the side of each pixel electrode 3, which overlaps the direction line is approximately 100 μm long. In this way, the overlap area is approximately 100 μm long. Also, the dielectric constants e in Table 1 above are for the insulation layer 33. The distances "w" and "d" are shown in the Figure 7, with the distance "w" which is the width of the overlap and the distance "d" the vertical separation between the pixel electrodes and the overlapping direction lines. Compare the values in Table 1 with a conventional coplanar LCD, in which the pixel electrodes are substantially coplanar with and separate from the address lines, such conventional LCD having a pixel-line capacitance of approximately 11.8 fF (caused partly by the LC material) when the electrodes are laterally separated from the direction lines by approximately 5 μm, and approximately 9.6 fF, when the lateral separation is approximately 10 μm. In this way, the high-aperture LCDs of Examples 1-8 have a greater pixel aperture ratio than conventional LCDs without suffering from substantially higher values of line-pixel capacitance. The capacitance values established in the above in Table 1 are obtained from the previous Cp ^ equation in combination, taking into consideration the effects of the capacitance in a known way.
The line pixel capacitance (fF) is less than about 20 fF, preferably less than or equal to about 12 fF, and more preferably less than, or equal to about 7.0 fF in accordance with this invention with overlapping areas and high pixel openings. Once given the above description, many other features, modifications and improvements, will become apparent, therefore, considered a part of this invention, the scope of which will be determined by the following claims. It is noted that in relation to this date, the best method known to the applicant to carry out the aforementioned invention is that which is clear from the present description of the invention. Having described the invention as above, property is claimed as contained in the following:

Claims (23)

1. A high aperture liquid crystal display, characterized in that it comprises: first and second substrates; a liquid crystal layer sandwiched between the first and second substrates; a disposition of thin film transistors (TFT) placed on the first substrate, the arrangement of the TFTs include a plurality of address lines connected to the TFT; an arrangement of substantially transparent pixel electrodes positioned on the first substrate, a plurality of the pixel electrodes in the pixel electrode arrangement overlapping at least one of the direction lines, thereby increasing the pixel aperture ratio of the LCD; an insulating photo-image forming layer placed on the first substrate, between the address lines and the pixel electrodes in at least the overlapping areas and the areas adjacent to the source electrodes of the TFT; and an image-forming isolator layer having a first group of paths defined therein by photo-imaging, wherein the pixel electrodes are in electrical communication with the corresponding TFT source electrodes, by means of the contact paths of the first group defined in the insulating layer.
2. The liquid crystal display according to claim 1, further characterized in that it comprises an auxiliary storage capacitor electrode, associated with each pixel electrode and a second group of contact paths defined in the insulating layer by the photo-formation of images and wherein each of the pixel electrodes is in electrical communication with a corresponding storage capacitor electrode, through one of the paths in the second group of the contact paths.
3. The liquid crystal display according to claim 1, characterized in that the insulating layer is a negative protective layer.
4. The liquid crystal display according to claim 1, characterized in that the insulating layer includes a 2-ethoxyethyl acetate and benzocyclobutene (BCB).
5. The liquid crystal display according to claim 1, characterized in that the dielectric constant e of the insulating layer is less than about 3.0.
6. The liquid crystal display according to claim 1, characterized in that the insulating layer includes an organic mixture of 2-ethoxyethyl acetate, a copolymer derived from methacrylate and polyfunctional acrylate.
7. The liquid crystal display according to claim 1, characterized in that the insulating layer is approximately 2-3 μm thick.
8. The liquid crystal display according to claim 1, characterized in that the insulating layer covers substantially the entire observation area of the screen, except for the contact paths formed therein.
9. The liquid crystal display according to claim 1, characterized in that the pixel aperture ratio of the LCD is at least about 68%.
10. The liquid crystal display according to claim 1, characterized in that the overlap distance or width is approximately 0-2 μm in the overlap areas and the address line capacitance of a pixel is less than approximately 12.0 fF, when the length of the overlap area is approximately 100 μm.
11. The liquid crystal display according to claim 10, characterized in that the capacitance is less than about 8.0 fF.
12. A TFT layout structure, characterized in that it comprises: an arrangement of the TFTs on a substrate, the TFTs are connected to a corresponding arrangement of pixel electrodes; the row and column direction lines on the substrate to direct the TFT; and an image-forming photo isolation means, positioned between (i) the pixel electrodes; and (ii) the direction lines to reduce crosstalk and allow the medium to be photo-formed in an image.
13. A liquid crystal display with a large pixel aperture ratio, characterized in that it comprises: a liquid crystal layer sandwiched between first and second substrates; an arrangement of thin film transistors and corresponding to the pixel electrodes mounted on the first substrate, each of the thin film transistors include a semiconductor layer, a gate electrode, connected to a gate address line, an electrode of drain connected to a drain direction line and a source electrode connected to one of the corresponding pixel electrodes and in which the pixel electrode connected to the source electrode overlaps the gate and drain direction lines along its longitudinal edges; and a substantially continuous insulating layer having a dielectric constant no greater than about 3.0, placed between the pixel electrode and the address lines in a thickness sufficient to reduce capacitive crosstalk on the screen by reducing the parasitic capacitance CpL of the line pixel direction-electrode in the areas of overlap.
14. The liquid crystal display according to claim 13, characterized in that the CpL is defined by the equation: 'PL where eQ is 8.85 x 10 ~ 14, F / cm, "d" is the thickness of the insulating layer in the overlapping areas and "A" is the area of the capacitor formed between the pixel electrode and the direction lines in the overlap area; and in which CpL is less than or equal to approximately 0.01 pF, when the pixel separation of the screen is approximately 150 μm, to reduce crosstalk in the display.
15. The liquid crystal display according to claim 13, characterized in that the thickness "d" of the insulating layer is at least about 1.5 μm in the overlapping areas.
16. The liquid crystal display according to claim 15, characterized in that "d" is about 2 to 3 μm in the overlapping areas and the insulating layer has a degree of planarization of at least about 90%.
17. The liquid crystal display according to claim 15, characterized in that the screen has a pixel aperture ratio of at least about 65% and a pixel spacing of about 40 to 500 μm.
The liquid crystal display according to claim 13, characterized in that the insulating layer includes benzocyclobutene (BCB) and has a dielectric constant e of about 2.7 or less.
19. A liquid crystal display, characterized in that it comprises: a layer of liquid crystal; a substantially transparent substrate, adjacent to the liquid crystal layer; a disposition of thin film transistors placed on the substrate, the thin film transistors connected to the address lines and which act as switching elements to energize the corresponding pixel electrodes; a substantially transparent planarization layer, placed on the transistor array, the planarization layer that is located between (i) the pixel electrodes; and (ii) the address lines; and wherein the planarization layer includes benzocyclobutene (BCB) and has a dielectric constant of less than about 3.0.
20. A method for manufacturing a semiconductor array based on thin film transistors (TFT), the method is characterized in that it comprises the steps of: providing a substantially transparent first substrate; forming an arrangement of the corresponding TFTs and address lines on the first substrate; depositing an insulating photo-forming layer, organic on both of the TFT array and the corresponding address lines; photo-forming of images of the insulating layer to form a first arrangement of paths or contact holes in it; and forming a disposition of electrode members on the first substrate, on the insulating, photo-forming layer of images, in such a way that the electrode members in the arrangement are in communication with the corresponding TFTs, through the first arrangement of paths or contact holes.
21. The method according to claim 20, further characterized in that it comprises the step of overlapping the direction lines with the electrode members, such that the insulating layer photo-formed with the image is placed between them to reduce crosstalk.
22. The method according to claim 21, further characterized in that it comprises the steps of (i) using the TFT array on a liquid crystal display and an image detector and (ii) forming the insulator layer to include one of BCB and acetate. 2-ethoxyethyl, photo-imagers.
23. The screen according to claim 19, characterized in that the BCB layer is not image-forming.
MX9602205A 1996-06-06 1996-06-06 Lod with increased pixel opening sizes. MX9602205A (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US08/470,271 1995-06-06
US47027196A 1996-06-06 1996-06-06

Publications (2)

Publication Number Publication Date
MXPA96002205A true MXPA96002205A (en) 1997-08-01
MX9602205A MX9602205A (en) 1997-08-30

Family

ID=38988509

Family Applications (1)

Application Number Title Priority Date Filing Date
MX9602205A MX9602205A (en) 1996-06-06 1996-06-06 Lod with increased pixel opening sizes.

Country Status (1)

Country Link
MX (1) MX9602205A (en)

Similar Documents

Publication Publication Date Title
CA2178232C (en) Lcd with bus lines overlapped by pixel electrodes and photo-imageable insulating layer therebetween
US6365916B1 (en) High aperture LCD with insulating color filters overlapping bus lines on active substrate
US6011274A (en) X-ray imager or LCD with bus lines overlapped by pixel electrodes and dual insulating layers therebetween
US6359672B2 (en) Method of making an LCD or X-ray imaging device with first and second insulating layers
KR100454186B1 (en) Thin film transistors with self-aligned transparent pixel electrode
US20020076845A1 (en) Manufacturing method for reflection type liquid crystal display
MXPA96002205A (en) Liquid crystal screen with common connection lines transferred by pixel electrodes and an insulating photo-image former layer between the
KR20080077492A (en) Display panel and method of manufacturing the same