[go: up one dir, main page]
More Web Proxy on the site http://driver.im/

Ciccazzo et al., 2015 - Google Patents

A SVM surrogate model-based method for parametric yield optimization

Ciccazzo et al., 2015

View PDF
Document ID
3979349660263117587
Author
Ciccazzo A
Di Pillo G
Latorre V
Publication year
Publication venue
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

External Links

Snippet

Yield optimization is a challenging topic in electronic circuit design. Methods for yield optimization based on Monte Carlo (MC) analysis of a circuit whose behavior is reproduced by simulations usually require too many time expensive simulations to be effective for …
Continue reading at www.actorventure.com (PDF) (other versions)

Classifications

    • GPHYSICS
    • G06COMPUTING; CALCULATING; COUNTING
    • G06FELECTRICAL DIGITAL DATA PROCESSING
    • G06F17/00Digital computing or data processing equipment or methods, specially adapted for specific functions
    • G06F17/50Computer-aided design
    • G06F17/5068Physical circuit design, e.g. layout for integrated circuits or printed circuit boards
    • G06F17/5081Layout analysis, e.g. layout verification, design rule check
    • GPHYSICS
    • G06COMPUTING; CALCULATING; COUNTING
    • G06FELECTRICAL DIGITAL DATA PROCESSING
    • G06F17/00Digital computing or data processing equipment or methods, specially adapted for specific functions
    • G06F17/50Computer-aided design
    • G06F17/5009Computer-aided design using simulation
    • G06F17/5036Computer-aided design using simulation for analog modelling, e.g. for circuits, spice programme, direct methods, relaxation methods
    • GPHYSICS
    • G06COMPUTING; CALCULATING; COUNTING
    • G06FELECTRICAL DIGITAL DATA PROCESSING
    • G06F2217/00Indexing scheme relating to computer aided design [CAD]
    • G06F2217/78Power analysis and optimization
    • GPHYSICS
    • G06COMPUTING; CALCULATING; COUNTING
    • G06QDATA PROCESSING SYSTEMS OR METHODS, SPECIALLY ADAPTED FOR ADMINISTRATIVE, COMMERCIAL, FINANCIAL, MANAGERIAL, SUPERVISORY OR FORECASTING PURPOSES; SYSTEMS OR METHODS SPECIALLY ADAPTED FOR ADMINISTRATIVE, COMMERCIAL, FINANCIAL, MANAGERIAL, SUPERVISORY OR FORECASTING PURPOSES, NOT OTHERWISE PROVIDED FOR
    • G06Q10/00Administration; Management
    • G06Q10/06Resources, workflows, human or project management, e.g. organising, planning, scheduling or allocating time, human or machine resources; Enterprise planning; Organisational models
    • G06Q10/063Operations research or analysis
    • GPHYSICS
    • G06COMPUTING; CALCULATING; COUNTING
    • G06FELECTRICAL DIGITAL DATA PROCESSING
    • G06F2217/00Indexing scheme relating to computer aided design [CAD]
    • G06F2217/12Design for manufacturability
    • GPHYSICS
    • G06COMPUTING; CALCULATING; COUNTING
    • G06FELECTRICAL DIGITAL DATA PROCESSING
    • G06F17/00Digital computing or data processing equipment or methods, specially adapted for specific functions
    • G06F17/20Handling natural language data
    • GPHYSICS
    • G06COMPUTING; CALCULATING; COUNTING
    • G06FELECTRICAL DIGITAL DATA PROCESSING
    • G06F2217/00Indexing scheme relating to computer aided design [CAD]
    • G06F2217/70Fault tolerant, i.e. transient fault suppression
    • GPHYSICS
    • G06COMPUTING; CALCULATING; COUNTING
    • G06FELECTRICAL DIGITAL DATA PROCESSING
    • G06F7/00Methods or arrangements for processing data by operating upon the order or content of the data handled
    • GPHYSICS
    • G06COMPUTING; CALCULATING; COUNTING
    • G06FELECTRICAL DIGITAL DATA PROCESSING
    • G06F1/00Details of data-processing equipment not covered by groups G06F3/00 - G06F13/00, e.g. cooling, packaging or power supply specially adapted for computer application
    • GPHYSICS
    • G06COMPUTING; CALCULATING; COUNTING
    • G06NCOMPUTER SYSTEMS BASED ON SPECIFIC COMPUTATIONAL MODELS
    • G06N99/00Subject matter not provided for in other groups of this subclass
    • GPHYSICS
    • G06COMPUTING; CALCULATING; COUNTING
    • G06FELECTRICAL DIGITAL DATA PROCESSING
    • G06F21/00Security arrangements for protecting computers, components thereof, programs or data against unauthorised activity

Similar Documents

Publication Publication Date Title
Ciccazzo et al. A SVM surrogate model-based method for parametric yield optimization
US20220207351A1 (en) Semiconductor design optimization using at least one neural network
US10949585B1 (en) System and method for predicting performance, power and area behavior of soft IP components in integrated circuit design
Ye et al. On-chip droop-induced circuit delay prediction based on support-vector machines
Genssler et al. Modeling and predicting transistor aging under workload dependency using machine learning
Ramprasath et al. A skew-normal canonical model for statistical static timing analysis
US6356861B1 (en) Deriving statistical device models from worst-case files
Hsu et al. In-placement clock-tree aware multi-bit flip-flop generation for power optimization
US8813006B1 (en) Accelerated characterization of circuits for within-die process variations
Ghavami et al. Reliable circuit design using a fast incremental-based gate sizing under process variation
Duan et al. Lifetime reliability-aware digital synthesis
Kannan et al. Activity-aware prediction of Critical Paths Aging in FDSOI technologies
Roy et al. Numerically convex forms and their application in gate sizing
Jungmann et al. TCAD-enabled machine learning—an efficient framework to build highly accurate and reliable models for semiconductor technology development and fabrication
Rakai et al. Buffer sizing for clock networks using robust geometric programming considering variations in buffer sizes
Abbas et al. Yield-driven power-delay-optimal CMOS full-adder design complying with automotive product specifications of PVT variations and NBTI degradations
Xu et al. An adaptive Copula function-based framework for fault detection in semiconductor wafer fabrication
US9348957B1 (en) Repetitive circuit simulation
Balaskas et al. Variability-aware approximate circuit synthesis via genetic optimization
Bhardwaj et al. A unified approach for full chip statistical timing and leakage analysis of nanoscale circuits considering intradie process variations
Hao et al. Intelligent and kernelized placement: A survey
Jyu et al. Statistical delay modeling in logic design and synthesis
Pidin Influence of Within-Die Transistor Characteristics Variation on FINFET Circuit Delay
Juan et al. Statistical thermal modeling and optimization considering leakage power variations
Yang et al. A selected inversion approach for locality driven vectorless power grid verification