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Azambuja et al., 2014 - Google Patents

Hybrid Fault Tolerance Techniques to Detect Transient Faults in Embedded Processors

Azambuja et al., 2014

Document ID
3701216769068908978
Author
Azambuja J
Kastensmidt F
Becker J
Publication year

External Links

Snippet

This book describes fault tolerance techniques based on software and hardware to create hybrid techniques. They are able to reduce overall performance degradation and increase error detection when associated with applications implemented in embedded processors …
Continue reading at books.google.com (other versions)

Classifications

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    • G06F17/5022—Logic simulation, e.g. for logic circuit operation
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    • G06F11/0706—Error or fault processing not based on redundancy, i.e. by taking additional measures to deal with the error or fault not making use of redundancy in operation, in hardware, or in data representation the processing taking place on a specific hardware platform or in a specific software environment
    • G06F11/0721—Error or fault processing not based on redundancy, i.e. by taking additional measures to deal with the error or fault not making use of redundancy in operation, in hardware, or in data representation the processing taking place on a specific hardware platform or in a specific software environment within a central processing unit [CPU]
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