[go: up one dir, main page]
More Web Proxy on the site http://driver.im/

Hauck et al., 1997 - Google Patents

An evaluation of bipartitioning techniques

Hauck et al., 1997

View PDF
Document ID
3511246016917167832
Author
Hauck S
Borriello G
Publication year
Publication venue
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

External Links

Snippet

Logic partitioning is an important issue in VLSI CAD, and has been an area of active research for at least the last 25 years. Numerous approaches have been developed and many different techniques have been combined for a wide range of applications. In this …
Continue reading at citeseerx.ist.psu.edu (PDF) (other versions)

Classifications

    • GPHYSICS
    • G06COMPUTING; CALCULATING; COUNTING
    • G06FELECTRICAL DIGITAL DATA PROCESSING
    • G06F17/00Digital computing or data processing equipment or methods, specially adapted for specific functions
    • G06F17/50Computer-aided design
    • G06F17/5045Circuit design
    • G06F17/505Logic synthesis, e.g. technology mapping, optimisation
    • GPHYSICS
    • G06COMPUTING; CALCULATING; COUNTING
    • G06FELECTRICAL DIGITAL DATA PROCESSING
    • G06F17/00Digital computing or data processing equipment or methods, specially adapted for specific functions
    • G06F17/50Computer-aided design
    • G06F17/5068Physical circuit design, e.g. layout for integrated circuits or printed circuit boards
    • G06F17/5077Routing
    • GPHYSICS
    • G06COMPUTING; CALCULATING; COUNTING
    • G06FELECTRICAL DIGITAL DATA PROCESSING
    • G06F17/00Digital computing or data processing equipment or methods, specially adapted for specific functions
    • G06F17/50Computer-aided design
    • G06F17/5068Physical circuit design, e.g. layout for integrated circuits or printed circuit boards
    • G06F17/5072Floorplanning, e.g. partitioning, placement
    • GPHYSICS
    • G06COMPUTING; CALCULATING; COUNTING
    • G06FELECTRICAL DIGITAL DATA PROCESSING
    • G06F17/00Digital computing or data processing equipment or methods, specially adapted for specific functions
    • G06F17/50Computer-aided design
    • G06F17/5045Circuit design
    • G06F17/5054Circuit design for user-programmable logic devices, e.g. field programmable gate arrays [FPGA]
    • GPHYSICS
    • G06COMPUTING; CALCULATING; COUNTING
    • G06FELECTRICAL DIGITAL DATA PROCESSING
    • G06F17/00Digital computing or data processing equipment or methods, specially adapted for specific functions
    • G06F17/50Computer-aided design
    • G06F17/5009Computer-aided design using simulation
    • G06F17/5022Logic simulation, e.g. for logic circuit operation
    • G06F17/5031Timing analysis
    • GPHYSICS
    • G06COMPUTING; CALCULATING; COUNTING
    • G06FELECTRICAL DIGITAL DATA PROCESSING
    • G06F17/00Digital computing or data processing equipment or methods, specially adapted for specific functions
    • G06F17/50Computer-aided design
    • G06F17/5009Computer-aided design using simulation
    • G06F17/5036Computer-aided design using simulation for analog modelling, e.g. for circuits, spice programme, direct methods, relaxation methods
    • GPHYSICS
    • G06COMPUTING; CALCULATING; COUNTING
    • G06FELECTRICAL DIGITAL DATA PROCESSING
    • G06F17/00Digital computing or data processing equipment or methods, specially adapted for specific functions
    • G06F17/30Information retrieval; Database structures therefor; File system structures therefor
    • G06F17/30286Information retrieval; Database structures therefor; File system structures therefor in structured data stores
    • G06F17/30386Retrieval requests
    • G06F17/30424Query processing
    • G06F17/30533Other types of queries
    • GPHYSICS
    • G06COMPUTING; CALCULATING; COUNTING
    • G06FELECTRICAL DIGITAL DATA PROCESSING
    • G06F17/00Digital computing or data processing equipment or methods, specially adapted for specific functions
    • G06F17/50Computer-aided design
    • G06F17/5068Physical circuit design, e.g. layout for integrated circuits or printed circuit boards
    • G06F17/5081Layout analysis, e.g. layout verification, design rule check
    • GPHYSICS
    • G06COMPUTING; CALCULATING; COUNTING
    • G06FELECTRICAL DIGITAL DATA PROCESSING
    • G06F17/00Digital computing or data processing equipment or methods, specially adapted for specific functions
    • G06F17/30Information retrieval; Database structures therefor; File system structures therefor
    • G06F17/30943Information retrieval; Database structures therefor; File system structures therefor details of database functions independent of the retrieved data type
    • G06F17/30946Information retrieval; Database structures therefor; File system structures therefor details of database functions independent of the retrieved data type indexing structures
    • GPHYSICS
    • G06COMPUTING; CALCULATING; COUNTING
    • G06FELECTRICAL DIGITAL DATA PROCESSING
    • G06F2217/00Indexing scheme relating to computer aided design [CAD]
    • G06F2217/78Power analysis and optimization
    • GPHYSICS
    • G06COMPUTING; CALCULATING; COUNTING
    • G06FELECTRICAL DIGITAL DATA PROCESSING
    • G06F2217/00Indexing scheme relating to computer aided design [CAD]
    • G06F2217/70Fault tolerant, i.e. transient fault suppression
    • GPHYSICS
    • G06COMPUTING; CALCULATING; COUNTING
    • G06FELECTRICAL DIGITAL DATA PROCESSING
    • G06F2217/00Indexing scheme relating to computer aided design [CAD]
    • G06F2217/08Multi-objective optimization
    • GPHYSICS
    • G06COMPUTING; CALCULATING; COUNTING
    • G06FELECTRICAL DIGITAL DATA PROCESSING
    • G06F7/00Methods or arrangements for processing data by operating upon the order or content of the data handled

Similar Documents

Publication Publication Date Title
Hauck et al. An evaluation of bipartitioning techniques
Cong et al. Cut ranking and pruning: Enabling a general and efficient FPGA mapping solution
Cong et al. Combinational logic synthesis for LUT based field programmable gate arrays
Cong et al. Matching-based methods for high-performance clock routing
Vemuri et al. BDD-based logic synthesis for LUT-based FPGAs
Maidee et al. Fast timing-driven partitioning-based placement for island style FPGAs
Lin et al. Placement-driven technology mapping for LUT-based FPGAs
Bozorgzadeh et al. Routability-driven packing: Metrics and algorithms for cluster-based FPGAs
Chowdhary et al. Extraction of functional regularity in datapath circuits
Jiang et al. Temporal partitioning data flow graphs for dynamically reconfigurable computing
Chen et al. Simultaneous timing driven clustering and placement for FPGAs
Cong et al. Structural gate decomposition for depth-optimal technology mapping in LUT-based FPGA designs
Wu et al. Generic ILP-based approaches for time-multiplexed FPGA partitioning
Alexander et al. An architecture-independent approach to FPGA routing based on multi-weighted graphs.
Hutton et al. Timing-driven placement for hierarchical programmable logic devices
Chen et al. Simultaneous logic decomposition with technology mapping in FPGA designs
Taghavi et al. Innovate or perish: FPGA physical design
Sankar Ultra-fast automatic placement for FPGAs
Cong et al. Performance-driven technology mapping for heterogeneous FPGAs
Brayton et al. An integrated technology mapping environment
Cong et al. A Theory on Partially-Dependent Functional Decomposition with Application in LUT-based FPGA
Liu et al. Timing‐Driven NonuniformDepopulation‐Based Clustering
Mahapatra et al. DFG partitioning algorithms for coarse grained reconfigurable array assisted RTL simulation accelerators
Swartz A high-speed timing-aware router for FPGAs
Sharma Place and Route Techniques for FPGA Architecture Advancement