Zorian, 2005 - Google Patents
Today's SOC test challengesZorian, 2005
- Document ID
- 346259199641448441
- Author
- Zorian Y
- Publication year
- Publication venue
- IEEE International Conference on Test, 2005.
External Links
Snippet
Today's SOC test challenges Page 1 Panel 6.4 1 INTERNATIONAL TEST CONFERENCE 0-7803-9039-3/$20.00
© 2005 IEEE Today’s SOC Test Challenges Yervant Zorian Virage Logic Corp, Fremont, USA
zorian@viragelogic.com A set of SoC Test challenges have been introduced a decade ago …
- 239000000243 solution 0 description 9
Classifications
-
- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/317—Testing of digital circuits
- G01R31/3181—Functional testing
- G01R31/3185—Reconfiguring for testing, e.g. LSSD, partitioning
- G01R31/318533—Reconfiguring for testing, e.g. LSSD, partitioning using scanning techniques, e.g. LSSD, Boundary Scan, JTAG
- G01R31/318536—Scan chain arrangements, e.g. connections, test bus, analog signals
-
- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/317—Testing of digital circuits
- G01R31/3181—Functional testing
- G01R31/3183—Generation of test inputs, e.g. test vectors, patterns or sequence
-
- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/317—Testing of digital circuits
- G01R31/31718—Logistic aspects, e.g. binning, selection, sorting of devices under test, tester/handler interaction networks, Test management software, e.g. software for test statistics or test evaluation, yield analysis
-
- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/2851—Testing of integrated circuits [IC]
-
- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/30—Marginal testing, e.g. varying supply voltage
- G01R31/3004—Current or voltage test
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING; COUNTING
- G06F—ELECTRICAL DIGITAL DATA PROCESSING
- G06F17/00—Digital computing or data processing equipment or methods, specially adapted for specific functions
- G06F17/50—Computer-aided design
- G06F17/5009—Computer-aided design using simulation
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING; COUNTING
- G06F—ELECTRICAL DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/22—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing
- G06F11/2205—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing using arrangements specific to the hardware being tested
- G06F11/2236—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing using arrangements specific to the hardware being tested to test CPU or processors
-
- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/2832—Specific tests of electronic circuits not provided for elsewhere
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING; COUNTING
- G06F—ELECTRICAL DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/22—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing
- G06F11/26—Functional testing
- G06F11/273—Tester hardware, i.e. output processing circuits
- G06F11/2733—Test interface between tester and unit under test
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING; COUNTING
- G06F—ELECTRICAL DIGITAL DATA PROCESSING
- G06F1/00—Details of data-processing equipment not covered by groups G06F3/00 - G06F13/00, e.g. cooling, packaging or power supply specially adapted for computer application
Similar Documents
Publication | Publication Date | Title |
---|---|---|
Zorian | Test requirements for embedded core-based systems and IEEE P1500 | |
Zorian et al. | Test of future system-on-chips | |
Marinissen et al. | Challenges in testing core-based system ICs | |
Vermeulen et al. | Core-based scan architecture for silicon debug | |
Zorian | Testing the monster chip | |
US7779381B2 (en) | Test generation for low power circuits | |
Su et al. | Transient power supply current monitoring—A new test method for CMOS VLSI circuits | |
Steininger | Testing and built-in self-test–A survey | |
WO2002093640A1 (en) | Method for evaluating system-on-chip (soc) having core as its base and soc structure using the evaluation method | |
Zorian | System-chip test strategies | |
Vermeulen et al. | Trends in testing integrated circuits | |
de Gyvez et al. | Integrated circuit manufacturability: the art of process and design integration | |
Hawkins et al. | The VLSI circuit test problem-a tutorial | |
Chaudhuri et al. | Built-in self-test of high-density and realistic ILV layouts in monolithic 3-D ICs | |
Taouil et al. | Post-bond interconnect test and diagnosis for 3-D memory stacked on logic | |
Zorian | Today's SOC test challenges | |
US11379644B1 (en) | IC chip test engine | |
Haring et al. | Blue Gene/L compute chip: Control, test, and bring-up infrastructure | |
US6968519B2 (en) | System and method for using IDDQ pattern generation for burn-in tests | |
Sarvi et al. | Automated BIST-based diagnostic solution for SOPC | |
Ghosh et al. | Shannon expansion based supply-gated logic for improved power and testability | |
Zorian | Emerging trends in VLSI test and diagnosis | |
Han et al. | Novel hierarchical test architecture for SOC test methodology using IEEE test standards | |
Hunter et al. | Design and implementation of the" G2" PowerPC/sup TM/603e-embedded microprocessor core | |
White et al. | Design for semiconductor manufacturing. Bibliography |