[go: up one dir, main page]
More Web Proxy on the site http://driver.im/

Zorian, 2005 - Google Patents

Today's SOC test challenges

Zorian, 2005

Document ID
346259199641448441
Author
Zorian Y
Publication year
Publication venue
IEEE International Conference on Test, 2005.

External Links

Snippet

Today's SOC test challenges Page 1 Panel 6.4 1 INTERNATIONAL TEST CONFERENCE 0-7803-9039-3/$20.00 © 2005 IEEE Today’s SOC Test Challenges Yervant Zorian Virage Logic Corp, Fremont, USA zorian@viragelogic.com A set of SoC Test challenges have been introduced a decade ago …
Continue reading at ieeexplore.ieee.org (other versions)

Classifications

    • GPHYSICS
    • G01MEASURING; TESTING
    • G01RMEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317Testing of digital circuits
    • G01R31/3181Functional testing
    • G01R31/3185Reconfiguring for testing, e.g. LSSD, partitioning
    • G01R31/318533Reconfiguring for testing, e.g. LSSD, partitioning using scanning techniques, e.g. LSSD, Boundary Scan, JTAG
    • G01R31/318536Scan chain arrangements, e.g. connections, test bus, analog signals
    • GPHYSICS
    • G01MEASURING; TESTING
    • G01RMEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317Testing of digital circuits
    • G01R31/3181Functional testing
    • G01R31/3183Generation of test inputs, e.g. test vectors, patterns or sequence
    • GPHYSICS
    • G01MEASURING; TESTING
    • G01RMEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317Testing of digital circuits
    • G01R31/31718Logistic aspects, e.g. binning, selection, sorting of devices under test, tester/handler interaction networks, Test management software, e.g. software for test statistics or test evaluation, yield analysis
    • GPHYSICS
    • G01MEASURING; TESTING
    • G01RMEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28Testing of electronic circuits, e.g. by signal tracer
    • G01R31/2851Testing of integrated circuits [IC]
    • GPHYSICS
    • G01MEASURING; TESTING
    • G01RMEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28Testing of electronic circuits, e.g. by signal tracer
    • G01R31/30Marginal testing, e.g. varying supply voltage
    • G01R31/3004Current or voltage test
    • GPHYSICS
    • G06COMPUTING; CALCULATING; COUNTING
    • G06FELECTRICAL DIGITAL DATA PROCESSING
    • G06F17/00Digital computing or data processing equipment or methods, specially adapted for specific functions
    • G06F17/50Computer-aided design
    • G06F17/5009Computer-aided design using simulation
    • GPHYSICS
    • G06COMPUTING; CALCULATING; COUNTING
    • G06FELECTRICAL DIGITAL DATA PROCESSING
    • G06F11/00Error detection; Error correction; Monitoring
    • G06F11/22Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing
    • G06F11/2205Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing using arrangements specific to the hardware being tested
    • G06F11/2236Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing using arrangements specific to the hardware being tested to test CPU or processors
    • GPHYSICS
    • G01MEASURING; TESTING
    • G01RMEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28Testing of electronic circuits, e.g. by signal tracer
    • G01R31/2832Specific tests of electronic circuits not provided for elsewhere
    • GPHYSICS
    • G06COMPUTING; CALCULATING; COUNTING
    • G06FELECTRICAL DIGITAL DATA PROCESSING
    • G06F11/00Error detection; Error correction; Monitoring
    • G06F11/22Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing
    • G06F11/26Functional testing
    • G06F11/273Tester hardware, i.e. output processing circuits
    • G06F11/2733Test interface between tester and unit under test
    • GPHYSICS
    • G06COMPUTING; CALCULATING; COUNTING
    • G06FELECTRICAL DIGITAL DATA PROCESSING
    • G06F1/00Details of data-processing equipment not covered by groups G06F3/00 - G06F13/00, e.g. cooling, packaging or power supply specially adapted for computer application

Similar Documents

Publication Publication Date Title
Zorian Test requirements for embedded core-based systems and IEEE P1500
Zorian et al. Test of future system-on-chips
Marinissen et al. Challenges in testing core-based system ICs
Vermeulen et al. Core-based scan architecture for silicon debug
Zorian Testing the monster chip
US7779381B2 (en) Test generation for low power circuits
Su et al. Transient power supply current monitoring—A new test method for CMOS VLSI circuits
Steininger Testing and built-in self-test–A survey
WO2002093640A1 (en) Method for evaluating system-on-chip (soc) having core as its base and soc structure using the evaluation method
Zorian System-chip test strategies
Vermeulen et al. Trends in testing integrated circuits
de Gyvez et al. Integrated circuit manufacturability: the art of process and design integration
Hawkins et al. The VLSI circuit test problem-a tutorial
Chaudhuri et al. Built-in self-test of high-density and realistic ILV layouts in monolithic 3-D ICs
Taouil et al. Post-bond interconnect test and diagnosis for 3-D memory stacked on logic
Zorian Today's SOC test challenges
US11379644B1 (en) IC chip test engine
Haring et al. Blue Gene/L compute chip: Control, test, and bring-up infrastructure
US6968519B2 (en) System and method for using IDDQ pattern generation for burn-in tests
Sarvi et al. Automated BIST-based diagnostic solution for SOPC
Ghosh et al. Shannon expansion based supply-gated logic for improved power and testability
Zorian Emerging trends in VLSI test and diagnosis
Han et al. Novel hierarchical test architecture for SOC test methodology using IEEE test standards
Hunter et al. Design and implementation of the" G2" PowerPC/sup TM/603e-embedded microprocessor core
White et al. Design for semiconductor manufacturing. Bibliography