Ying et al., 2019 - Google Patents
Area optimization of MPRM circuits using approximate computingYing et al., 2019
- Document ID
- 3404749386001640591
- Author
- Ying Q
- Wang L
- Chu Z
- Xia Y
- Publication year
- Publication venue
- 2019 IEEE 13th International Conference on ASIC (ASICON)
External Links
Snippet
Approximate computing is a novel paradigm design of Integrated Circuits (ICs). By introducing an acceptable amount of inaccuracy, the area, power, and delay of a circuit can be significantly reduced. In this paper, an approximate logic synthesis (ALS) method target …
- 238000005457 optimization 0 title abstract description 12
Classifications
-
- H—ELECTRICITY
- H03—BASIC ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
- H03M13/37—Decoding methods or techniques, not specific to the particular type of coding provided for in groups H03M13/03 - H03M13/35
- H03M13/39—Sequence estimation, i.e. using statistical methods for the reconstruction of the original codes
- H03M13/41—Sequence estimation, i.e. using statistical methods for the reconstruction of the original codes using the Viterbi algorithm or Viterbi processors
- H03M13/4107—Sequence estimation, i.e. using statistical methods for the reconstruction of the original codes using the Viterbi algorithm or Viterbi processors implementing add, compare, select [ACS] operations
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING; COUNTING
- G06F—ELECTRICAL DIGITAL DATA PROCESSING
- G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
- G06F7/38—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
- G06F7/48—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING; COUNTING
- G06F—ELECTRICAL DIGITAL DATA PROCESSING
- G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
- G06F7/58—Random or pseudo-random number generators
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING; COUNTING
- G06F—ELECTRICAL DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/07—Error detection; Error correction; Monitoring responding to the occurence of a fault, e.g. fault tolerance
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING; COUNTING
- G06F—ELECTRICAL DIGITAL DATA PROCESSING
- G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
- G06F7/02—Comparing digital values
-
- H—ELECTRICITY
- H03—BASIC ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M7/00—Conversion of a code where information is represented by a given sequence or number of digits to a code where the same information or similar information or a subset of information is represented by a different sequence or number of digits
- H03M7/30—Compression; Expansion; Suppression of unnecessary data, e.g. redundancy reduction
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING; COUNTING
- G06F—ELECTRICAL DIGITAL DATA PROCESSING
- G06F17/00—Digital computing or data processing equipment or methods, specially adapted for specific functions
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING; COUNTING
- G06F—ELECTRICAL DIGITAL DATA PROCESSING
- G06F2207/00—Indexing scheme relating to methods or arrangements for processing data by operating upon the order or content of the data handled
-
- H—ELECTRICITY
- H03—BASIC ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
- H03K19/20—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits characterised by logic function, e.g. AND, OR, NOR, NOT circuits
- H03K19/21—EXCLUSIVE-OR circuits, i.e. giving output if input signal exists at only one input; COINCIDENCE circuits, i.e. giving output only if all input signals are identical
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L9/00—Cryptographic mechanisms or cryptographic arrangements for secret or secure communication
- H04L9/06—Cryptographic mechanisms or cryptographic arrangements for secret or secure communication the encryption apparatus using shift registers or memories for block-wise or stream coding, e.g. DES systems or RC4; Hash functions; Pseudorandom sequence generators
Similar Documents
Publication | Publication Date | Title |
---|---|---|
Sarkis et al. | Fast polar decoders: Algorithm and implementation | |
Miller et al. | Reducing reversible circuit cost by adding lines | |
Lin et al. | An efficient list decoder architecture for polar codes | |
Lin et al. | A high throughput list decoder architecture for polar codes | |
Xiong et al. | A multimode area-efficient SCL polar decoder | |
Sun et al. | Post-processing methods for improving coding gain in belief propagation decoding of polar codes | |
CN106940638B (en) | Hardware architecture of binary original code addition and subtraction arithmetic unit | |
Lee et al. | A node-reliability based CRC-aided successive cancellation list polar decoder architecture combined with post-processing | |
US20210385094A1 (en) | Physical unclonable function based true random number generator, method for generating true random numbers, and associated electronic device | |
Ying et al. | Area optimization of MPRM circuits using approximate computing | |
Hiller et al. | Seesaw: An area-optimized FPGA viterbi decoder for PUFs | |
Ramprasad et al. | Signal coding for low power: Fundamental limits and practical realizations | |
Shrivas et al. | Design and performance analysis of 1 bit full adder using GDI technique in nanometer era | |
Hassani et al. | A novel ultra low power accuracy configurable adder at transistor level | |
Taher et al. | A machine learning based hard fault recuperation model for approximate hardware accelerators | |
CN117081751A (en) | High-reliability quantitative response arbiter type PUF structure | |
Wang et al. | Power optimization for FPRM logic using approximate computing technique | |
US6938172B2 (en) | Data transformation for the reduction of power and noise in CMOS structures | |
Zhang et al. | An accurate and time-efficient subtractor by cross format coding in stochastic computing | |
Lekatsas et al. | Approximate arithmetic coding for bus transition reduction in low power designs | |
Devi et al. | An asynchronous low power and high performance VLSI architecture for Viterbi decoder implemented with quasi delay insensitive templates | |
Naveen et al. | Low power Viterbi decoder design based on reversible logic gates | |
Murotiya et al. | CNTFET-based low power design of 4-input ternary XOR function | |
Mantravadi | Design of Area Efficient Low Power Ever Mixed Logic Line Decoders and Comparator | |
US5309494A (en) | Circuit configuration for generating logical butterfly structures |