[go: up one dir, main page]
More Web Proxy on the site http://driver.im/

Ryan et al., 2007 - Google Patents

Analyzing and modeling process balance for sub-threshold circuit design

Ryan et al., 2007

View PDF
Document ID
3347645174440220677
Author
Ryan J
Wang J
Calhoun B
Publication year
Publication venue
Proceedings of the 17th ACM Great Lakes symposium on VLSI

External Links

Snippet

This paper describes the strong effects on sub-threshold digital circuit operation of the ratio of PMOS and NMOS current in a given process. We define the concept of process balance/imbalance as describing this ratio and explain the impact ofdifferent circuit and …
Continue reading at rlpvlsi.ece.virginia.edu (PDF) (other versions)

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/41—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming static cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger
    • G11C11/412—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming static cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger using field-effect transistors only
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/41—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming static cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger
    • G11C11/413—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing, timing, power reduction
    • G11C11/417—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing, timing, power reduction for memory cells of the field-effect type
    • G11C11/419—Read-write circuits
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING; COUNTING
    • G06F—ELECTRICAL DIGITAL DATA PROCESSING
    • G06F17/00—Digital computing or data processing equipment or methods, specially adapted for specific functions
    • G06F17/50—Computer-aided design
    • G06F17/5009—Computer-aided design using simulation

Similar Documents

Publication Publication Date Title
Islam et al. Variability aware low leakage reliable SRAM cell design technique
Pal et al. Variation tolerant differential 8T SRAM cell for ultralow power applications
Calhoun et al. Sub-threshold circuit design with shrinking CMOS devices
Sharma et al. VLSI scaling methods and low power CMOS buffer circuit
Roy et al. Design of differential TG based 8T SRAM cell for ultralow-power applications
Kim et al. An 8T subthreshold SRAM cell utilizing reverse short channel effect for write margin and read performance improvement
Raychowdhury et al. A feasibility study of subthreshold SRAM across technology generations
Kumar et al. Process evaluation in FinFET based 7T SRAM cell
Islam et al. Variability analysis of 6t and 7t sram cell in sub-45nm technology
Tripathi et al. Implementation of low-power 6T SRAM cell using MTCMOS technique
Mushtaq et al. Performance analysis for reliable nanoscaled FinFET logic circuits
Ryan et al. Analyzing and modeling process balance for sub-threshold circuit design
CN101533424B (en) Gate replacing method for easing aging of integrated circuit and reducing leakage power consumption
Mukhopadhyay et al. Reduction of parametric failures in sub-100-nm SRAM array using body bias
Ferré et al. Characterization of leakage power in CMOS technologies
Carlson Mechanism of Increase in SRAM $ V_ {\min} $ Due to Negative-Bias Temperature Instability
Abu-Rahma et al. Variability in nanometer technologies and impact on SRAM
Chen et al. Robust design of high fan-in/out subthreshold circuits
Pal et al. Device bias technique to improve design metrics of 6T SRAM cell for subthreshold operation
Gupta et al. Device-circuit co-optimization for robust design of FinFET-based SRAMs
Yadav et al. Double-gate FinFET process variation aware 10T SRAM cell topology design and analysis
Zhang et al. 28-nm latch-type sense amplifier modification for coupling suppression
Samandari-Rad Design and analysis of robust variability-aware SRAM to predict optimal access-time to achieve yield enhancement in future nano-scaled CMOS
Chen et al. FDSOI SRAM cells for low power design at 22nm technology node
Islam et al. Single-ended 6T SRAM cell to improve dynamic power dissipation by decreasing activity factor