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Monteiro, 2019 - Google Patents

Algorithms to improve area density utilization, routability and timing during detailed placement and legalization of VLSI circuits

Monteiro, 2019

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Document ID
329736069776702689
Author
Monteiro J
Publication year

External Links

Snippet

Placement is a challenging stage in the Very Large-Scale Integration (VLSI) physical design flow. In modern VLSI designs, several design restrictions have been imposed to address the complexity of advanced Complementary Metal-Oxide Semiconductor (CMOS) fabrication …
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Classifications

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    • G06F17/5081—Layout analysis, e.g. layout verification, design rule check
    • G—PHYSICS
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    • G06F17/5072—Floorplanning, e.g. partitioning, placement
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