[go: up one dir, main page]
More Web Proxy on the site http://driver.im/

Priest et al., 2005 - Google Patents

Feasibility study of a sip for high performance and reliability product application

Priest et al., 2005

Document ID
3021332940847207799
Author
Priest J
Ahmad M
Li L
Xue J
Brillhart M
Publication year
Publication venue
2005 Conference on High Density Microsystem Design and Packaging and Component Failure Analysis

External Links

Snippet

For specific applications, there can be significant performance advantages when using a SiP (system in package). With the proper silicon functional partitioning, well controlled interconnect medium, and well tuned interface design; the data bandwidth can be increased …
Continue reading at ieeexplore.ieee.org (other versions)

Classifications

    • H—ELECTRICITY
    • H01—BASIC ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—BASIC ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
    • H—ELECTRICITY
    • H01—BASIC ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
    • H—ELECTRICITY
    • H01—BASIC ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/301—Electrical effects
    • H—ELECTRICITY
    • H01—BASIC ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation; Temperature sensing arrangements
    • H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
    • H01L23/367—Cooling facilitated by shape of device
    • H—ELECTRICITY
    • H01—BASIC ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H—ELECTRICITY
    • H01—BASIC ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING; COUNTING
    • G06F—ELECTRICAL DIGITAL DATA PROCESSING
    • G06F17/00—Digital computing or data processing equipment or methods, specially adapted for specific functions
    • G06F17/50—Computer-aided design

Similar Documents

Publication Publication Date Title
Mahajan et al. Embedded multidie interconnect bridge—A localized, high-density multichip packaging interconnect
Tummala Multichip packaging-a tutorial
EP0559366A1 (en) Stackable three-dimensional multiple chip semiconductor device and method for making the same
US20040164401A1 (en) Module with adhesively attached heat sink
US7439170B1 (en) Design structure for final via designs for chip stress reduction
Blackshear et al. The evolution of build-up package technology and its design challenges
Zhang et al. Benchmarking digital die-to-die channels in 2.5-D and 3-D heterogeneous integration platforms
US20080191704A1 (en) Method to Improve Isolation of an Open Net Fault in an Interposer Mounted Module
Schaper Design of multichip modules
Priest et al. Feasibility study of a sip for high performance and reliability product application
Priest et al. Design optimization of a high performance FCAMP package for manufacturability and reliability
Sudo Present and future directions for multichip module technologies
Darnauer et al. Electrical evaluation of flip-chip package alternatives for next generation microprocessors
US20070080441A1 (en) Thermal expansion compensation graded IC package
Wu et al. Interconnect and package design of a heterogeneous stacked-silicon FPGA
Katopis et al. MCM-C/D design for the CMOS implementation of the S/390 system
Chung et al. Area array packaging technologies for high-performance computer workstations and multiprocessors
Harvey et al. Packaging the cell broadband engine microprocessor for supercomputer applications
Yang et al. Signal integrity and design consideration of an MCM for video graphic acceleration
Raghupathy et al. Best engineering practice for thermal characterization of stacked dice FPGA devices
Fjelstad et al. Wafer level packaging of compliant, chip size ICs
Dang et al. Simulation-Based Impedance Characterization of PDN in High-Performance Multi-Chip HTCC Packages for Avionics
Lin et al. Physical Design Flow for 3D/CoWoS® Stacked IC s
Switky et al. A 1024-pin plastic ball grid array for flip chip die
Peltier et al. A discussion of a GaAs MCM fabricated at MicroModule Systems through the multichip module designers' access service (MIDAS)