[go: up one dir, main page]
More Web Proxy on the site http://driver.im/

Zhou et al., 2009 - Google Patents

Pipeline FFT architectures optimized for FPGAs

Zhou et al., 2009

View PDF @Full View
Document ID
3026140753027953392
Author
Zhou B
Peng Y
Hwang D
Publication year
Publication venue
International Journal of Reconfigurable Computing

External Links

Snippet

This paper presents optimized implementations of two different pipeline FFT processors on Xilinx Spartan‐3 and Virtex‐4 FPGAs. Different optimization techniques and rounding schemes were explored. The implementation results achieved better performance with lower …
Continue reading at onlinelibrary.wiley.com (PDF) (other versions)

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING; COUNTING
    • G06F—ELECTRICAL DIGITAL DATA PROCESSING
    • G06F17/00—Digital computing or data processing equipment or methods, specially adapted for specific functions
    • G06F17/10—Complex mathematical operations
    • G06F17/14—Fourier, Walsh or analogous domain transformations, e.g. Laplace, Hilbert, Karhunen-Loeve, transforms
    • G06F17/141—Discrete Fourier transforms
    • G06F17/142—Fast Fourier transforms, e.g. using a Cooley-Tukey type algorithm
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING; COUNTING
    • G06F—ELECTRICAL DIGITAL DATA PROCESSING
    • G06F17/00—Digital computing or data processing equipment or methods, specially adapted for specific functions
    • G06F17/10—Complex mathematical operations
    • G06F17/14—Fourier, Walsh or analogous domain transformations, e.g. Laplace, Hilbert, Karhunen-Loeve, transforms
    • G06F17/147—Discrete orthonormal transforms, e.g. discrete cosine transform, discrete sine transform, and variations therefrom, e.g. modified discrete cosine transform, integer transforms approximating the discrete cosine transform
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING; COUNTING
    • G06F—ELECTRICAL DIGITAL DATA PROCESSING
    • G06F17/00—Digital computing or data processing equipment or methods, specially adapted for specific functions
    • G06F17/30—Information retrieval; Database structures therefor; File system structures therefor
    • G06F17/30861—Retrieval from the Internet, e.g. browsers
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING; COUNTING
    • G06F—ELECTRICAL DIGITAL DATA PROCESSING
    • G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F7/38—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
    • G06F7/48—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
    • G06F7/52—Multiplying; Dividing
    • G06F7/523—Multiplying only
    • G06F7/53—Multiplying only in parallel-parallel fashion, i.e. both operands being entered in parallel
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING; COUNTING
    • G06F—ELECTRICAL DIGITAL DATA PROCESSING
    • G06F17/00—Digital computing or data processing equipment or methods, specially adapted for specific functions
    • G06F17/50—Computer-aided design
    • G06F17/5009—Computer-aided design using simulation
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING; COUNTING
    • G06F—ELECTRICAL DIGITAL DATA PROCESSING
    • G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F7/38—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
    • G06F7/48—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
    • G06F7/544—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices for evaluating functions by calculation
    • G06F7/5443—Sum of products
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING; COUNTING
    • G06F—ELECTRICAL DIGITAL DATA PROCESSING
    • G06F17/00—Digital computing or data processing equipment or methods, specially adapted for specific functions
    • G06F17/50—Computer-aided design
    • G06F17/5045—Circuit design
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING; COUNTING
    • G06F—ELECTRICAL DIGITAL DATA PROCESSING
    • G06F1/00—Details of data-processing equipment not covered by groups G06F3/00 - G06F13/00, e.g. cooling, packaging or power supply specially adapted for computer application
    • G06F1/16—Constructional details or arrangements
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING; COUNTING
    • G06F—ELECTRICAL DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for programme control, e.g. control unit
    • G06F9/06—Arrangements for programme control, e.g. control unit using stored programme, i.e. using internal store of processing equipment to receive and retain programme
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING; COUNTING
    • G06F—ELECTRICAL DIGITAL DATA PROCESSING
    • G06F2207/00—Indexing scheme relating to methods or arrangements for processing data by operating upon the order or content of the data handled
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING; COUNTING
    • G06F—ELECTRICAL DIGITAL DATA PROCESSING
    • G06F15/00—Digital computers in general; Data processing equipment in general

Similar Documents

Publication Publication Date Title
Zhou et al. Pipeline FFT architectures optimized for FPGAs
Wang et al. A combined SDC-SDF architecture for normal I/O pipelined radix-2 FFT
Lin et al. Design space exploration for sparse matrix‐matrix multiplication on FPGAs
Zhong et al. A power-scalable reconfigurable FFT/IFFT IC based on a multi-processor ring
Ingemarsson et al. Efficient FPGA mapping of pipeline SDF FFT cores
Arunachalam et al. Efficient VLSI implementation of FFT for orthogonal frequency division multiplexing applications
Elango et al. VLSI implementation of an area and energy efficient FFT/IFFT core for MIMO-OFDM applications
Pan et al. Efficient digit‐serial modular multiplication algorithm on FPGA
Ingemarsson et al. SFF—The single-stream FPGA-optimized feedforward FFT hardware architecture
Elango et al. Hardware implementation of FFT/IFFT algorithms incorporating efficient computational elements
Ferreira et al. Low‐power fast Fourier transform hardware architecture combining a split‐radix butterfly and efficient adder compressors
Chang et al. An OFDM-specified lossless FFT architecture
Parhi Approaches to low-power implementations of DSP systems
Beulet Paul et al. Low power reconfigurable FP-FFT core with an array of folded DA butterflies
Godi et al. Design optimisation of multiplier‐free parallel pipelined FFT on field programmable gate array
Wang et al. Hybrid wordlength optimization methods of pipelined FFT processors
Mirzaei et al. Layout aware optimization of high speed fixed coefficient FIR filters for FPGAs
Joshi et al. Distributed arithmetic based split-radix FFT
Garcia et al. VLSI configurable delay commutator for a pipeline split radix FFT architecture
Mukherjee et al. A novel architecture of area efficient FFT algorithm for FPGA implementation
Zhou et al. Implementations and optimizations of pipeline FFTs on Xilinx FPGAs
Locharla et al. Variable length mixed radix MDC FFT/IFFT processor for MIMO‐OFDM application
Hazarika et al. Energy efficient VLSI architecture of real‐valued serial pipelined FFT
Das et al. Area–time–energy efficient architecture of CBNS‐based fast Fourier transform
Vergara et al. A 195K FFT/s (256-points) high performance FFT/IFFT processor for OFDM applications