Schwaderer et al., 2012 - Google Patents
OCP Signal Groups and PhasesSchwaderer et al., 2012
- Document ID
- 2747883503709292169
- Author
- Schwaderer W
- Schwaderer W
- Publication year
- Publication venue
- Introduction to Open Core Protocol: Fastpath to System-on-Chip Design
External Links
Snippet
OCP Signal Groups and Phases | SpringerLink Skip to main content Advertisement
SpringerLink Account Menu Find a journal Publish with us Track your research Search Cart
Book cover Introduction to Open Core Protocol pp 85–96Cite as 1.Home 2.Introduction to Open …
- 230000004044 response 0 description 56
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING; COUNTING
- G06F—ELECTRICAL DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
- G06F13/40—Bus structure
- G06F13/4004—Coupling between buses
- G06F13/4027—Coupling between buses using bus bridges
- G06F13/405—Coupling between buses using bus bridges where the bridge performs a synchronising function
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING; COUNTING
- G06F—ELECTRICAL DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
- G06F13/40—Bus structure
- G06F13/4004—Coupling between buses
- G06F13/4022—Coupling between buses using switching circuits, e.g. switching matrix, connection or expansion network
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING; COUNTING
- G06F—ELECTRICAL DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for programme control, e.g. control unit
- G06F9/06—Arrangements for programme control, e.g. control unit using stored programme, i.e. using internal store of processing equipment to receive and retain programme
- G06F9/46—Multiprogramming arrangements
- G06F9/52—Programme synchronisation; Mutual exclusion, e.g. by means of semaphores; Contention for resources among tasks
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING; COUNTING
- G06F—ELECTRICAL DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
- G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
- G06F13/4204—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus
- G06F13/4234—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus being a memory bus
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING; COUNTING
- G06F—ELECTRICAL DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/14—Handling requests for interconnection or transfer
- G06F13/16—Handling requests for interconnection or transfer for access to memory bus
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING; COUNTING
- G06F—ELECTRICAL DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/14—Handling requests for interconnection or transfer
- G06F13/36—Handling requests for interconnection or transfer for access to common bus or bus system
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING; COUNTING
- G06F—ELECTRICAL DIGITAL DATA PROCESSING
- G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
- G06F3/06—Digital input from or digital output to record carriers, e.g. RAID, emulated record carriers, networked record carriers
- G06F3/0601—Dedicated interfaces to storage systems
- G06F3/0628—Dedicated interfaces to storage systems making use of a particular technique
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING; COUNTING
- G06F—ELECTRICAL DIGITAL DATA PROCESSING
- G06F17/00—Digital computing or data processing equipment or methods, specially adapted for specific functions
- G06F17/30—Information retrieval; Database structures therefor; File system structures therefor
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING; COUNTING
- G06F—ELECTRICAL DIGITAL DATA PROCESSING
- G06F15/00—Digital computers in general; Data processing equipment in general
- G06F15/16—Combinations of two or more digital computers each having at least an arithmetic unit, a programme unit and a register, e.g. for a simultaneous processing of several programmes
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING; COUNTING
- G06F—ELECTRICAL DIGITAL DATA PROCESSING
- G06F21/00—Security arrangements for protecting computers, components thereof, programs or data against unauthorised activity
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING; COUNTING
- G06F—ELECTRICAL DIGITAL DATA PROCESSING
- G06F1/00—Details of data-processing equipment not covered by groups G06F3/00 - G06F13/00, e.g. cooling, packaging or power supply specially adapted for computer application
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING; COUNTING
- G06Q—DATA PROCESSING SYSTEMS OR METHODS, SPECIALLY ADAPTED FOR ADMINISTRATIVE, COMMERCIAL, FINANCIAL, MANAGERIAL, SUPERVISORY OR FORECASTING PURPOSES; SYSTEMS OR METHODS SPECIALLY ADAPTED FOR ADMINISTRATIVE, COMMERCIAL, FINANCIAL, MANAGERIAL, SUPERVISORY OR FORECASTING PURPOSES, NOT OTHERWISE PROVIDED FOR
- G06Q10/00—Administration; Management
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN109564556B (en) | Memory controller arbiter with stripe and read/write transaction management | |
| CN107924375B (en) | Command arbitration for high-speed memory interface | |
| US7457905B2 (en) | Method for request transaction ordering in OCP bus to AXI bus bridge design | |
| TW400483B (en) | High performance symmetric arbitration protocol with support for I/O requirements | |
| US5625779A (en) | Arbitration signaling mechanism to prevent deadlock guarantee access latency, and guarantee acquisition latency for an expansion bridge | |
| US7308522B2 (en) | Method and apparatus to allow dynamic variation of ordering enforcement between transactions in a strongly ordered computer interconnect | |
| Shrivastav et al. | Performance comparison of AMBA bus-based system-on-chip communication protocol | |
| WO2011025955A1 (en) | Memory controller page management devices, systems, and methods | |
| JP2008027305A (en) | Data processor | |
| JP3954011B2 (en) | Method and computer system for communicating between subsystems | |
| JP2024515055A (en) | Seamlessly integrated microcontroller chip | |
| CN100432972C (en) | Mechanism for preserving producer-consumer ordering across an unordered interface | |
| US8886844B2 (en) | Efficient scheduling of read and write transactions in dynamic memory controllers | |
| CN101814012A (en) | SDRAM (Synchronous Dynamic Random Access Memory) memory structure and data reading and writing method | |
| TWI330811B (en) | Apparatus and method for sparse line write transactions | |
| CN102591817B (en) | Multi-bus bridge controller and implementing method thereof | |
| CN108667628A (en) | A kind of interface switching device and interface conversion method | |
| Schwaderer et al. | OCP Signal Groups and Phases | |
| CN110023919A (en) | Methods, devices and systems for delivery type memory non-in processing structure write-in affairs | |
| US20030131175A1 (en) | Method and apparatus for ensuring multi-threaded transaction ordering in a strongly ordered computer interconnect | |
| US7370139B2 (en) | Methods and structures for efficient storage of task file information in serial ATA environments | |
| Noami et al. | High performance AXI4 interface protocol for multi-core memory controller on SoC | |
| Schwaderer et al. | OCP Tags, Threads, and Connections | |
| JP4642531B2 (en) | Arbitration of data requests | |
| US20050246464A1 (en) | Method of arbitration which allows requestors from multiple frequency domains |