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Tavva et al., 2010 - Google Patents

Variation tolerant 9T SRAM cell design

Tavva et al., 2010

Document ID
2653744879258078096
Author
Tavva S
Kudithipudi D
Publication year
Publication venue
Proceedings of the 20th symposium on Great lakes symposium on VLSI

External Links

Snippet

Nanoscale SRAM memory design has become increasingly challenging due to the reducing noise margins and increased sensitivity to threshold voltage variations. These issues oppose our ability to achieve stable bitcells and acceptable performance while maintaining …
Continue reading at dl.acm.org (other versions)

Classifications

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    • G11C11/41—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming static cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger
    • G11C11/413—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing, timing, power reduction
    • G11C11/417—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing, timing, power reduction for memory cells of the field-effect type
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