[go: up one dir, main page]
More Web Proxy on the site http://driver.im/

Liu et al., 2018 - Google Patents

Back-end layout reflection for test chip design

Liu et al., 2018

Document ID
2553407200760131515
Author
Liu Z
Blanton R
Publication year
Publication venue
2018 IEEE 36th International Conference on Computer Design (ICCD)

External Links

Snippet

At advanced technology nodes, complex interactions between layout features and the process can lead to manufacturability issues that reduce yield. Due to the huge number of layout geometries inherent to random logic, logic-only test chips are increasingly employed …
Continue reading at ieeexplore.ieee.org (other versions)

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING; COUNTING
    • G06F—ELECTRICAL DIGITAL DATA PROCESSING
    • G06F17/00—Digital computing or data processing equipment or methods, specially adapted for specific functions
    • G06F17/50—Computer-aided design
    • G06F17/5068—Physical circuit design, e.g. layout for integrated circuits or printed circuit boards
    • G06F17/5081—Layout analysis, e.g. layout verification, design rule check
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING; COUNTING
    • G06F—ELECTRICAL DIGITAL DATA PROCESSING
    • G06F17/00—Digital computing or data processing equipment or methods, specially adapted for specific functions
    • G06F17/50—Computer-aided design
    • G06F17/5068—Physical circuit design, e.g. layout for integrated circuits or printed circuit boards
    • G06F17/5077—Routing
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING; COUNTING
    • G06F—ELECTRICAL DIGITAL DATA PROCESSING
    • G06F17/00—Digital computing or data processing equipment or methods, specially adapted for specific functions
    • G06F17/50—Computer-aided design
    • G06F17/5068—Physical circuit design, e.g. layout for integrated circuits or printed circuit boards
    • G06F17/5072—Floorplanning, e.g. partitioning, placement
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING; COUNTING
    • G06F—ELECTRICAL DIGITAL DATA PROCESSING
    • G06F17/00—Digital computing or data processing equipment or methods, specially adapted for specific functions
    • G06F17/50—Computer-aided design
    • G06F17/5009—Computer-aided design using simulation
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING; COUNTING
    • G06F—ELECTRICAL DIGITAL DATA PROCESSING
    • G06F17/00—Digital computing or data processing equipment or methods, specially adapted for specific functions
    • G06F17/50—Computer-aided design
    • G06F17/5045—Circuit design
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING; COUNTING
    • G06F—ELECTRICAL DIGITAL DATA PROCESSING
    • G06F2217/00—Indexing scheme relating to computer aided design [CAD]
    • G06F2217/12—Design for manufacturability
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317—Testing of digital circuits
    • G01R31/3181—Functional testing
    • G01R31/3183—Generation of test inputs, e.g. test vectors, patterns or sequence
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING; COUNTING
    • G06F—ELECTRICAL DIGITAL DATA PROCESSING
    • G06F2217/00—Indexing scheme relating to computer aided design [CAD]
    • G06F2217/70—Fault tolerant, i.e. transient fault suppression
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317—Testing of digital circuits
    • G01R31/3181—Functional testing
    • G01R31/3185—Reconfiguring for testing, e.g. LSSD, partitioning
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING; COUNTING
    • G06T—IMAGE DATA PROCESSING OR GENERATION, IN GENERAL
    • G06T7/00—Image analysis
    • G06T7/0002—Inspection of images, e.g. flaw detection
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317—Testing of digital circuits
    • G01R31/31718—Logistic aspects, e.g. binning, selection, sorting of devices under test, tester/handler interaction networks, Test management software, e.g. software for test statistics or test evaluation, yield analysis
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING; COUNTING
    • G06T—IMAGE DATA PROCESSING OR GENERATION, IN GENERAL
    • G06T2207/00—Indexing scheme for image analysis or image enhancement
    • G06T2207/30—Subject of image; Context of image processing
    • G06T2207/30108—Industrial image inspection
    • G06T2207/30148—Semiconductor; IC; Wafer

Similar Documents

Publication Publication Date Title
KR101789004B1 (en) Methods and systems for utilizing design data in combination with inspection data
US6418551B1 (en) Design rule checking tools and methods that use waiver layout patterns to waive unwanted dimensional check violations
US8429582B1 (en) Methods, systems, and articles of manufacture for smart pattern capturing and layout fixing
US9430606B2 (en) Failure analysis and inline defect characterization
KR102389065B1 (en) Systems and methods for systematic physical failure analysis (pfa) fault localization
JP2006512767A (en) Yield improvement
US11714944B2 (en) Optimization of physical cell placement for integrated circuits
Khare et al. Accurate estimation of defect-related yield loss in reconfigurable VLSI circuits
US11714129B2 (en) Observation point injection for integrated circuit testing
Segal et al. Using electrical bitmap results from embedded memory to enhance yield
US20070114396A1 (en) Critical area calculation method and yield calculation method
US20060026540A1 (en) Electro-migration (EM) and Voltage (IR) Drop Analysis of Integrated Circuit (IC) Designs
Liu et al. Back-end layout reflection for test chip design
US10198548B2 (en) Identifying the defective layer of a yield excursion through the statistical analysis of scan diagnosis results
Liu et al. Front-end layout reflection for test chip design
Tang et al. Diagnosing timing related cell internal defects for FinFET technology
Gaitonde et al. Hierarchical mapping of spot defects to catastrophic faults-design and applications
Fynan et al. Logic characterization vehicle design reflection via layout rewiring
Ciplickas et al. Predictive yield modeling of VLSIC's
US20070266358A1 (en) Yield calculation method
US6745358B1 (en) Enhanced fault coverage
Liu A Test Chip Design for Automatic Insertion of Logic Circuit Demographics
Chen et al. A non-intrusive and accurate inspection method for segment delay variabilities
Madge New test paradigms for yield and manufacturability
Lin et al. A local parallel search approach for memory failure pattern identification