Gupta et al., 2023 - Google Patents
Standard Cell Library Design of 2: 1 Mux Using 45nm TechnologyGupta et al., 2023
- Document ID
- 2559051435078170972
- Author
- Gupta A
- Singh M
- Jaiswal R
- Goel D
- Singh K
- Publication year
- Publication venue
- 2023 International Conference on Next Generation Electronics (NEleX)
External Links
Snippet
Rapid technique development aimed at significantly reducing power consumption or dissipation is required for low-power VLSI designs. We suggest creating a unique multiplexer design to satisfy the rising need for low-power multiplexer cells to alleviate the …
- 238000005516 engineering process 0 title description 16
Classifications
-
- H—ELECTRICITY
- H03—BASIC ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
- H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
- H03K19/08—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices
- H03K19/094—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices using field-effect transistors
- H03K19/096—Synchronous circuits, i.e. using clock signals
-
- H—ELECTRICITY
- H03—BASIC ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
- H03K19/0175—Coupling arrangements; Interface arrangements
- H03K19/0185—Coupling arrangements; Interface arrangements using field effect transistors only
- H03K19/018507—Interface arrangements
-
- H—ELECTRICITY
- H03—BASIC ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
- H03K19/0008—Arrangements for reducing power consumption
- H03K19/0016—Arrangements for reducing power consumption by using a control or a clock signal, e.g. in order to apply power supply
-
- H—ELECTRICITY
- H03—BASIC ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
- H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
- H03K19/173—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components
-
- H—ELECTRICITY
- H03—BASIC ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
- H03K19/003—Modifications for increasing the reliability for protection
- H03K19/00323—Delay compensation
-
- H—ELECTRICITY
- H03—BASIC ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K3/00—Circuits for generating electric pulses; Monostable, bistable or multistable circuits
- H03K3/02—Generators characterised by the type of circuit or by the means used for producing pulses
- H03K3/353—Generators characterised by the type of circuit or by the means used for producing pulses by the use, as active elements, of field-effect transistors with internal or external positive feedback
-
- H—ELECTRICITY
- H03—BASIC ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
- H03K19/01—Modifications for accelerating switching
- H03K19/017—Modifications for accelerating switching in field-effect transistor circuits
-
- H—ELECTRICITY
- H03—BASIC ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K17/00—Electronic switching or gating, i.e. not by contact-making or -braking
- H03K17/51—Electronic switching or gating, i.e. not by contact-making or -braking characterised by the components used
- H03K17/56—Electronic switching or gating, i.e. not by contact-making or -braking characterised by the components used using semiconductor devices
- H03K17/687—Electronic switching or gating, i.e. not by contact-making or -braking characterised by the components used using semiconductor devices using field-effect transistors
- H03K17/693—Switching arrangements with several input- or output-terminals
-
- H—ELECTRICITY
- H03—BASIC ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
- H03K19/20—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits characterised by logic function, e.g. AND, OR, NOR, NOT circuits
- H03K19/21—EXCLUSIVE-OR circuits, i.e. giving output if input signal exists at only one input; COINCIDENCE circuits, i.e. giving output only if all input signals are identical
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING; COUNTING
- G06F—ELECTRICAL DIGITAL DATA PROCESSING
- G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
- G06F7/38—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
- G06F7/48—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
- G06F7/50—Adding; Subtracting
- G06F7/505—Adding; Subtracting in bit-parallel fashion, i.e. having a different digit-handling circuit for each denomination
- G06F7/506—Adding; Subtracting in bit-parallel fashion, i.e. having a different digit-handling circuit for each denomination with simultaneous carry generation for, or propagation over, two or more stages
-
- H—ELECTRICITY
- H03—BASIC ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K3/00—Circuits for generating electric pulses; Monostable, bistable or multistable circuits
- H03K3/01—Details
- H03K3/012—Modifications of generator to improve response time or to decrease power consumption
-
- H—ELECTRICITY
- H03—BASIC ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K5/00—Manipulating pulses not covered by one of the other main groups in this subclass
Similar Documents
Publication | Publication Date | Title |
---|---|---|
Foroutan et al. | Design of two Low-Power full adder cells using GDI structure and hybrid CMOS logic style | |
US8207758B2 (en) | Ultra-low power multi-threshold asynchronous circuit design | |
Sharma et al. | Low power 8-bit ALU design using full adder and multiplexer | |
KR102039810B1 (en) | Apparatus and methods for leakage current reduction in integrated circuits | |
Zhou et al. | Bit-Wise MTNCL: An ultra-low power bit-wise pipelined asynchronous circuit design methodology | |
Kamsani et al. | A low power multiplexer based pass transistor logic full adder | |
Gupta et al. | Analysis and optimization of active power and delay of 10T full adder using power gating technique at 45 nm technology | |
Gupta et al. | Standard Cell Library Design of 2: 1 Mux Using 45nm Technology | |
Al Zahrani et al. | Glitch-free design for multi-threshold CMOS NCL circuits | |
Navi et al. | An energy efficient full adder cell for low voltage | |
Lee et al. | Low power null convention logic circuit design based on DCVSL | |
US7986166B1 (en) | Clock buffer circuit | |
Kim et al. | A leakage tolerant high fan-in dynamic circuit design technique | |
US6040717A (en) | FRCPG: Forecasted restoration complementary pass gates | |
Jeong et al. | Robust high-performance low-power carry select adder | |
Di et al. | Ultra-low power multi-threshold asynchronous circuit design | |
Sivagnaname et al. | Controlled-load limited switch dynamic logic circuit | |
US20080061836A1 (en) | Current Mirror and Parallel Logic Evaluation | |
Kumre | Power and delay analysis of one bit adders | |
Rajalakshmi et al. | Exploring Performance Characteristics of Static and Dynamic CMOS Designs Using Cadence Tools | |
Kumar et al. | Low-Power High-Speed Double Gate 1-bit Full Adder Cell | |
Vardhan et al. | Design and Implementation of Low Power NAND Gate Based Combinational Circuits Using FinFET Technique | |
Martin et al. | Leakage power reduction in data driven dynamic logic circuits | |
Adam et al. | Low power CMOS logic families | |
Asyaei | A new circuit scheme for wide dynamic circuits |