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Hekmatpour et al., 2005 - Google Patents

Block-based schema-driven assertion generation for functional verification

Hekmatpour et al., 2005

Document ID
2387855076707957963
Author
Hekmatpour A
Salehi A
Publication year
Publication venue
14th Asian Test Symposium (ATS'05)

External Links

Snippet

Current assertion-based verification frameworks provide utilities to define assertions which are exercised during simulation. The traditional verification bottleneck of test generation, simulation, debug, and coverage analysis has been shifted but not eliminated. Defining …
Continue reading at ieeexplore.ieee.org (other versions)

Classifications

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    • G06F—ELECTRICAL DIGITAL DATA PROCESSING
    • G06F17/00—Digital computing or data processing equipment or methods, specially adapted for specific functions
    • G06F17/50—Computer-aided design
    • G06F17/5009—Computer-aided design using simulation
    • G06F17/5022—Logic simulation, e.g. for logic circuit operation
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING; COUNTING
    • G06F—ELECTRICAL DIGITAL DATA PROCESSING
    • G06F17/00—Digital computing or data processing equipment or methods, specially adapted for specific functions
    • G06F17/50—Computer-aided design
    • G06F17/5009—Computer-aided design using simulation
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    • G—PHYSICS
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    • G06F17/5045—Circuit design
    • G06F17/505—Logic synthesis, e.g. technology mapping, optimisation
    • G—PHYSICS
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    • G06F17/5045—Circuit design
    • G06F17/5054—Circuit design for user-programmable logic devices, e.g. field programmable gate arrays [FPGA]
    • G—PHYSICS
    • G01—MEASURING; TESTING
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    • G01R31/3183—Generation of test inputs, e.g. test vectors, patterns or sequence
    • G01R31/318342—Generation of test inputs, e.g. test vectors, patterns or sequence by preliminary fault modelling, e.g. analysis, simulation
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    • G01R31/3185—Reconfiguring for testing, e.g. LSSD, partitioning
    • G—PHYSICS
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