Japa et al., 2020 - Google Patents
Low area overhead DPA countermeasure exploiting tunnel transistor‐based random number generatorJapa et al., 2020
View PDF- Document ID
- 2320058770122222194
- Author
- Japa A
- Kumar Majumder M
- Sahoo S
- Vaddi R
- Publication year
- Publication venue
- IET Circuits, Devices & Systems
External Links
Snippet
Differential power analysis (DPA) has become an efficient side channel attack that obtains a secret key from the extracted power traces. Several traditional CMOS‐based DPA countermeasures resulted in high area overhead and performance degradation. This study …
- 238000004458 analytical method 0 abstract description 8
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING; COUNTING
- G06F—ELECTRICAL DIGITAL DATA PROCESSING
- G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
- G06F7/58—Random or pseudo-random number generators
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING; COUNTING
- G06F—ELECTRICAL DIGITAL DATA PROCESSING
- G06F17/00—Digital computing or data processing equipment or methods, specially adapted for specific functions
- G06F17/50—Computer-aided design
- G06F17/5009—Computer-aided design using simulation
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING; COUNTING
- G06F—ELECTRICAL DIGITAL DATA PROCESSING
- G06F17/00—Digital computing or data processing equipment or methods, specially adapted for specific functions
- G06F17/30—Information retrieval; Database structures therefor; File system structures therefor
- G06F17/30861—Retrieval from the Internet, e.g. browsers
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING; COUNTING
- G06F—ELECTRICAL DIGITAL DATA PROCESSING
- G06F21/00—Security arrangements for protecting computers, components thereof, programs or data against unauthorised activity
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L9/00—Cryptographic mechanisms or cryptographic arrangements for secret or secure communication
- H04L9/06—Cryptographic mechanisms or cryptographic arrangements for secret or secure communication the encryption apparatus using shift registers or memories for block-wise or stream coding, e.g. DES systems or RC4; Hash functions; Pseudorandom sequence generators
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L9/00—Cryptographic mechanisms or cryptographic arrangements for secret or secure communication
- H04L9/08—Key distribution or management, e.g. generation, sharing or updating, of cryptographic keys or passwords
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L2209/00—Additional information or applications relating to cryptographic mechanisms or cryptographic arrangements for secret or secure communication H04L9/00
- H04L2209/12—Details relating to cryptographic hardware or logic circuitry
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING; COUNTING
- G06N—COMPUTER SYSTEMS BASED ON SPECIFIC COMPUTATIONAL MODELS
- G06N99/00—Subject matter not provided for in other groups of this subclass
-
- H—ELECTRICITY
- H03—BASIC ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K3/00—Circuits for generating electric pulses; Monostable, bistable or multistable circuits
- H03K3/02—Generators characterised by the type of circuit or by the means used for producing pulses
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING; COUNTING
- G06F—ELECTRICAL DIGITAL DATA PROCESSING
- G06F2207/00—Indexing scheme relating to methods or arrangements for processing data by operating upon the order or content of the data handled
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING; COUNTING
- G06F—ELECTRICAL DIGITAL DATA PROCESSING
- G06F1/00—Details of data-processing equipment not covered by groups G06F3/00 - G06F13/00, e.g. cooling, packaging or power supply specially adapted for computer application
Similar Documents
Publication | Publication Date | Title |
---|---|---|
Halak | Physically unclonable functions | |
Alioto | Trends in hardware security: From basics to ASICs | |
Tung et al. | Low‐power high‐speed full adder for portable electronic applications | |
Yanambaka et al. | Making use of manufacturing process variations: A dopingless transistor based-PUF for hardware-assisted security | |
Jiang et al. | Low‐cost single event double‐upset tolerant latch design | |
Bi et al. | Tunnel FET current mode logic for DPA-resilient circuit designs | |
Abutaleb | A novel true random number generator based on QCA nanocomputing | |
Dokania et al. | Circuit‐level design technique to mitigate impact of process, voltage and temperature variations in complementary metal‐oxide semiconductor full adder cells | |
Garg et al. | Gate diffusion input based 4‐bit Vedic multiplier design | |
Khan et al. | An ultra-low power, reconfigurable, aging resilient RO PUF for IoT applications | |
Mohanty et al. | RTN in scaled transistors for on-chip random seed generation | |
Ahmad et al. | A novel idea of pseudo-code generator in quantum-dot cellular automata (QCA) | |
Bi et al. | Enhancing hardware security with emerging transistor technologies | |
Yan et al. | High‐performance, low‐cost, and highly reliable radiation hardened latch design | |
Hoang et al. | Design of ultra‐low power AES encryption cores with silicon demonstration in SOTB CMOS process | |
Rahman et al. | Reliability vs. security: Challenges and opportunities for developing reliable and secure integrated circuits | |
Monteiro et al. | Low‐power secure S‐box circuit using charge‐sharing symmetric adiabatic logic for advanced encryption standard hardware design | |
Sahoo et al. | A novel aging tolerant RO-PUF for low power application | |
Ashok et al. | Charge balancing symmetric pre‐resolve adiabatic logic against power analysis attacks | |
Kotipalli et al. | Asynchronous Advanced Encryption Standard Hardware with Random Noise Injection for Improved Side‐Channel Attack Resistance | |
Bheemana et al. | Negative capacitance FET based energy efficient and DPA attack resilient ultra-light weight block cipher design | |
Japa et al. | Tunnel FET‐based ultra‐lightweight reconfigurable TRNG and PUF design for resource‐constrained internet of things | |
Ni et al. | Pi puf: a processor-intrinsic puf for iot | |
Japa et al. | Low area overhead DPA countermeasure exploiting tunnel transistor‐based random number generator | |
Japa et al. | Tunnel FET ambipolarity‐based energy efficient and robust true random number generator against reverse engineering attacks |