[go: up one dir, main page]
More Web Proxy on the site http://driver.im/

Speicher et al., 2018 - Google Patents

Advanced modeling methodology for expedient rf soc verification and performance estimation

Speicher et al., 2018

Document ID
2150375553640402450
Author
Speicher F
Meier J
Beyerstedt C
Wunderlich R
Heinen S
Publication year
Publication venue
2018 15th International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design (SMACD)

External Links

Snippet

While the complexity of modern RF systems on chip grows significantly, the methods for functional verification can not hold pace. Powerful tools, that are available for the verification of purely digital systems are missing for analog/mixed-signal systems. This paper proposes …
Continue reading at ieeexplore.ieee.org (other versions)

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING; COUNTING
    • G06F—ELECTRICAL DIGITAL DATA PROCESSING
    • G06F17/00—Digital computing or data processing equipment or methods, specially adapted for specific functions
    • G06F17/50—Computer-aided design
    • G06F17/5009—Computer-aided design using simulation
    • G06F17/5036—Computer-aided design using simulation for analog modelling, e.g. for circuits, spice programme, direct methods, relaxation methods
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING; COUNTING
    • G06F—ELECTRICAL DIGITAL DATA PROCESSING
    • G06F17/00—Digital computing or data processing equipment or methods, specially adapted for specific functions
    • G06F17/50—Computer-aided design
    • G06F17/5009—Computer-aided design using simulation
    • G06F17/5022—Logic simulation, e.g. for logic circuit operation
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317—Testing of digital circuits
    • G01R31/3181—Functional testing
    • G01R31/3183—Generation of test inputs, e.g. test vectors, patterns or sequence
    • G01R31/318342—Generation of test inputs, e.g. test vectors, patterns or sequence by preliminary fault modelling, e.g. analysis, simulation
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING; COUNTING
    • G06F—ELECTRICAL DIGITAL DATA PROCESSING
    • G06F17/00—Digital computing or data processing equipment or methods, specially adapted for specific functions
    • G06F17/50—Computer-aided design
    • G06F17/5068—Physical circuit design, e.g. layout for integrated circuits or printed circuit boards
    • G06F17/5081—Layout analysis, e.g. layout verification, design rule check
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING; COUNTING
    • G06F—ELECTRICAL DIGITAL DATA PROCESSING
    • G06F17/00—Digital computing or data processing equipment or methods, specially adapted for specific functions
    • G06F17/50—Computer-aided design
    • G06F17/5045—Circuit design
    • G06F17/5054—Circuit design for user-programmable logic devices, e.g. field programmable gate arrays [FPGA]
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING; COUNTING
    • G06F—ELECTRICAL DIGITAL DATA PROCESSING
    • G06F17/00—Digital computing or data processing equipment or methods, specially adapted for specific functions
    • G06F17/50—Computer-aided design
    • G06F17/5045—Circuit design
    • G06F17/505—Logic synthesis, e.g. technology mapping, optimisation
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/2832—Specific tests of electronic circuits not provided for elsewhere
    • G01R31/2836—Fault-finding or characterising
    • G01R31/2839—Fault-finding or characterising using signal generators, power supplies or circuit analysers
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317—Testing of digital circuits
    • G01R31/3181—Functional testing
    • G01R31/3185—Reconfiguring for testing, e.g. LSSD, partitioning
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317—Testing of digital circuits
    • G01R31/3181—Functional testing
    • G01R31/319—Tester hardware, i.e. output processing circuit
    • G01R31/31903—Tester hardware, i.e. output processing circuit tester configuration
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING; COUNTING
    • G06F—ELECTRICAL DIGITAL DATA PROCESSING
    • G06F2217/00—Indexing scheme relating to computer aided design [CAD]
    • G06F2217/78—Power analysis and optimization
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING; COUNTING
    • G06F—ELECTRICAL DIGITAL DATA PROCESSING
    • G06F2217/00—Indexing scheme relating to computer aided design [CAD]
    • G06F2217/70—Fault tolerant, i.e. transient fault suppression
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING; COUNTING
    • G06F—ELECTRICAL DIGITAL DATA PROCESSING
    • G06F8/00—Arrangements for software engineering
    • G06F8/70—Software maintenance or management

Similar Documents

Publication Publication Date Title
Nenzi et al. Ngspice users manual version 23
US7295961B2 (en) Method for generating a circuit model
Chakravarthi A practical approach to VLSI system on chip (SoC) design
JP2017516223A (en) Computer-implemented system and method for translation of electronic design verification commands
Speicher et al. Advanced modeling methodology for expedient rf soc verification and performance estimation
Linaro et al. PanSuite: A free simulation environment for the analysis of hybrid electrical power systems
Akbay et al. Alternate test of RF front ends with IP constraints: Frequency domain test generation and validation
Gütschow et al. Setting limits on supersymmetry using simplified models
Meier et al. Modeling Power Supply Noise Effects for System-Level Simulation of $\Delta\Sigma $-ADCs
Kim et al. Leveraging designer's intent: A path toward simpler analog CAD tools
Schlottmann et al. FPAA empowering cooperative analog-digital signal processing
Kimura et al. Trusted verification test bench development for phase-locked loop (PLL) hardware insertion
Olivadese et al. DC-compliant small-signal macromodels of non-linear circuit blocks
Rahaman et al. Analysis & design of different astable multivibrator circuits for various applications in communication system
US8131521B1 (en) Block specific harmonic balance analysis system
Devarajegowda et al. A mutually-exclusive deployment of formal and simulation techniques using proof-core analysis
Pooja et al. Verification of interconnection IP for automobile applications using system verilog and UVM
Speicher et al. Ams verification methodology regarding supply modulation in rf socs induced by digital standard cells
Mons et al. SCERNE, an efficient CAD tool for the modeling of RF and Mixed blocks
Oh et al. System-level verification platform using systemverilog layered testbench & systemC OOP
Bhattacharya et al. MATLAB-Open Source Tool Based Framework for Test Generation for Digital Circuits Using Evolutionary Algorithms
US20230267257A1 (en) Automated verification of integrated circuits
Lin et al. 5D Hindmarsh Rose neural network fast synchronization based on FPGA
Zou et al. Application of Quartus II and FPGA Technology in Experiment of Principles of Computer Composition
Rosenfeld Issues for mixed-signal CAD-tester interface