[go: up one dir, main page]
More Web Proxy on the site http://driver.im/

Mirabella et al., 2021 - Google Patents

Testing single via related defects in digital VLSI designs

Mirabella et al., 2021

Document ID
2009668401707661125
Author
Mirabella N
Ricci M
Calà I
Lanza R
Grosso M
Publication year
Publication venue
Microelectronics Reliability

External Links

Snippet

In integrated circuit designs, the conductive connections between different layers are known as vias or cuts. Such structures are critical for digital circuit manufacturing, as they represent a common defect location. A well-established DfM/DfR rule suggests replicating every via …
Continue reading at www.sciencedirect.com (other versions)

Classifications

    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317—Testing of digital circuits
    • G01R31/3181—Functional testing
    • G01R31/3183—Generation of test inputs, e.g. test vectors, patterns or sequence
    • G01R31/318342—Generation of test inputs, e.g. test vectors, patterns or sequence by preliminary fault modelling, e.g. analysis, simulation
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317—Testing of digital circuits
    • G01R31/3181—Functional testing
    • G01R31/3185—Reconfiguring for testing, e.g. LSSD, partitioning
    • G01R31/318533—Reconfiguring for testing, e.g. LSSD, partitioning using scanning techniques, e.g. LSSD, Boundary Scan, JTAG
    • G01R31/318583—Design for test
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317—Testing of digital circuits
    • G01R31/31718—Logistic aspects, e.g. binning, selection, sorting of devices under test, tester/handler interaction networks, Test management software, e.g. software for test statistics or test evaluation, yield analysis
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/2851—Testing of integrated circuits [IC]
    • G01R31/2853—Electrical testing of internal connections or -isolation, e.g. latch-up or chip-to-lead connections
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING; COUNTING
    • G06F—ELECTRICAL DIGITAL DATA PROCESSING
    • G06F17/00—Digital computing or data processing equipment or methods, specially adapted for specific functions
    • G06F17/50—Computer-aided design
    • G06F17/5068—Physical circuit design, e.g. layout for integrated circuits or printed circuit boards
    • G06F17/5081—Layout analysis, e.g. layout verification, design rule check
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/30—Marginal testing, e.g. varying supply voltage
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/2832—Specific tests of electronic circuits not provided for elsewhere
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING; COUNTING
    • G06F—ELECTRICAL DIGITAL DATA PROCESSING
    • G06F17/00—Digital computing or data processing equipment or methods, specially adapted for specific functions
    • G06F17/50—Computer-aided design
    • G06F17/5009—Computer-aided design using simulation
    • G06F17/5022—Logic simulation, e.g. for logic circuit operation
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/302—Contactless testing
    • G01R31/308—Contactless testing using non-ionising electromagnetic radiation, e.g. optical radiation
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/02—Testing of electric apparatus, lines or components, for short-circuits, discontinuities, leakage of current, or incorrect line connection
    • G01R31/04—Testing connections, e.g. of plugs, of non-disconnectable joints
    • G01R31/043—Testing connections, e.g. of plugs, of non-disconnectable joints of releaseable connections, e.g. terminals mounted on a printed circuit board
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING; COUNTING
    • G06F—ELECTRICAL DIGITAL DATA PROCESSING
    • G06F2217/00—Indexing scheme relating to computer aided design [CAD]
    • G06F2217/70—Fault tolerant, i.e. transient fault suppression
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING; COUNTING
    • G06F—ELECTRICAL DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/22—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R1/00—Details of instruments or arrangements of the types included in groups G01R5/00 - G01R13/00 and G01R31/00
    • G01R1/02—General constructional details

Similar Documents

Publication Publication Date Title
Hapke et al. Cell-aware test
Jha et al. Testing of digital systems
US7870519B2 (en) Method for determining features associated with fails of integrated circuits
JP4322509B2 (en) Failure detection rate calculation device and failure detection rate calculation method
Hapke et al. Defect-oriented test: Effectiveness in high volume manufacturing
Blanton et al. Logic characterization vehicle design for maximal information extraction for yield learning
Tam et al. Physically-aware analysis of systematic defects in integrated circuits
Mirabella et al. Testing single via related defects in digital VLSI designs
Tehranipoor et al. Nanometer technology designs: High-quality delay tests
US11579194B1 (en) Utilizing single cycle ATPG test patterns to detect multicycle cell-aware defects
Gearhardt et al. Improving fault isolation using iterative diagnosis
US6781151B2 (en) Failure analysis vehicle
Tam et al. SLIDER: Simulation of layout-injected defects for electrical responses
Nelson et al. Automatic classification of bridge defects
Mirabella et al. On the test of single via related defects in digital VLSI designs
US11429776B1 (en) Fault rules files for testing an IC chip
US11461520B1 (en) SDD ATPG using fault rules files, SDF and node slack for testing an IC chip
Appello et al. Yield analysis of logic circuits
Auvray et al. Evolution of navigation and simulation tools in failure analysis
Vogels et al. Benchmarking diagnosis algorithms with a diverse set of IC deformations
Tam et al. Automated failure population creation for validating integrated circuit diagnosis methods
US11893336B1 (en) Utilizing transition ATPG test patterns to detect multicycle faults and/or defects in an IC chip
Bhattacherjee et al. CAD Navigation Principles
US11435401B1 (en) Timed transition cell-aware ATPG using fault rule files and SDF for testing an IC chip
Balachandran et al. Expediting ramp-to-volume production