[go: up one dir, main page]
More Web Proxy on the site http://driver.im/

Baklouti et al., 2009 - Google Patents

Study and integration of a parametric neighbouring interconnection network in a massively parallel architecture on FPGA

Baklouti et al., 2009

View PDF
Document ID
18371567588105768622
Author
Baklouti M
Abid M
Marquet P
Dekeyser J
Publication year
Publication venue
2009 IEEE/ACS International Conference on Computer Systems and Applications

External Links

Snippet

Single instruction multiple data processors are increasingly used in embedded systems for multimedia applications because of their area and energy-efficiency. Neighboring communications between the processing elements are a key issue in SIMD processors …
Continue reading at www.ceslab.org (PDF) (other versions)

Classifications

    • GPHYSICS
    • G06COMPUTING; CALCULATING; COUNTING
    • G06FELECTRICAL DIGITAL DATA PROCESSING
    • G06F15/00Digital computers in general; Data processing equipment in general
    • G06F15/16Combinations of two or more digital computers each having at least an arithmetic unit, a programme unit and a register, e.g. for a simultaneous processing of several programmes
    • G06F15/163Interprocessor communication
    • G06F15/173Interprocessor communication using an interconnection network, e.g. matrix, shuffle, pyramid, star, snowflake
    • G06F15/17356Indirect interconnection networks
    • G06F15/17368Indirect interconnection networks non hierarchical topologies
    • G06F15/17381Two dimensional, e.g. mesh, torus
    • GPHYSICS
    • G06COMPUTING; CALCULATING; COUNTING
    • G06FELECTRICAL DIGITAL DATA PROCESSING
    • G06F15/00Digital computers in general; Data processing equipment in general
    • G06F15/76Architectures of general purpose stored programme computers
    • G06F15/80Architectures of general purpose stored programme computers comprising an array of processing units with common control, e.g. single instruction multiple data processors
    • G06F15/8007Architectures of general purpose stored programme computers comprising an array of processing units with common control, e.g. single instruction multiple data processors single instruction multiple data [SIMD] multiprocessors
    • G06F15/8023Two dimensional arrays, e.g. mesh, torus
    • GPHYSICS
    • G06COMPUTING; CALCULATING; COUNTING
    • G06FELECTRICAL DIGITAL DATA PROCESSING
    • G06F15/00Digital computers in general; Data processing equipment in general
    • G06F15/16Combinations of two or more digital computers each having at least an arithmetic unit, a programme unit and a register, e.g. for a simultaneous processing of several programmes
    • G06F15/163Interprocessor communication
    • G06F15/173Interprocessor communication using an interconnection network, e.g. matrix, shuffle, pyramid, star, snowflake
    • G06F15/17337Direct connection machines, e.g. completely connected computers, point to point communication networks
    • GPHYSICS
    • G06COMPUTING; CALCULATING; COUNTING
    • G06FELECTRICAL DIGITAL DATA PROCESSING
    • G06F15/00Digital computers in general; Data processing equipment in general
    • G06F15/76Architectures of general purpose stored programme computers
    • G06F15/78Architectures of general purpose stored programme computers comprising a single central processing unit
    • G06F15/7867Architectures of general purpose stored programme computers comprising a single central processing unit with reconfigurable architecture
    • GPHYSICS
    • G06COMPUTING; CALCULATING; COUNTING
    • G06FELECTRICAL DIGITAL DATA PROCESSING
    • G06F9/00Arrangements for programme control, e.g. control unit
    • G06F9/06Arrangements for programme control, e.g. control unit using stored programme, i.e. using internal store of processing equipment to receive and retain programme
    • G06F9/30Arrangements for executing machine-instructions, e.g. instruction decode
    • G06F9/38Concurrent instruction execution, e.g. pipeline, look ahead
    • G06F9/3885Concurrent instruction execution, e.g. pipeline, look ahead using a plurality of independent parallel functional units
    • GPHYSICS
    • G06COMPUTING; CALCULATING; COUNTING
    • G06FELECTRICAL DIGITAL DATA PROCESSING
    • G06F9/00Arrangements for programme control, e.g. control unit
    • G06F9/06Arrangements for programme control, e.g. control unit using stored programme, i.e. using internal store of processing equipment to receive and retain programme
    • G06F9/46Multiprogramming arrangements
    • G06F9/50Allocation of resources, e.g. of the central processing unit [CPU]
    • G06F9/5061Partitioning or combining of resources
    • GPHYSICS
    • G06COMPUTING; CALCULATING; COUNTING
    • G06FELECTRICAL DIGITAL DATA PROCESSING
    • G06F9/00Arrangements for programme control, e.g. control unit
    • G06F9/06Arrangements for programme control, e.g. control unit using stored programme, i.e. using internal store of processing equipment to receive and retain programme
    • G06F9/30Arrangements for executing machine-instructions, e.g. instruction decode
    • G06F9/30003Arrangements for executing specific machine instructions
    • G06F9/30007Arrangements for executing specific machine instructions to perform operations on data operands
    • GPHYSICS
    • G06COMPUTING; CALCULATING; COUNTING
    • G06FELECTRICAL DIGITAL DATA PROCESSING
    • G06F17/00Digital computing or data processing equipment or methods, specially adapted for specific functions
    • G06F17/50Computer-aided design
    • G06F17/5045Circuit design
    • GPHYSICS
    • G06COMPUTING; CALCULATING; COUNTING
    • G06FELECTRICAL DIGITAL DATA PROCESSING
    • G06F11/00Error detection; Error correction; Monitoring
    • G06F11/07Error detection; Error correction; Monitoring responding to the occurence of a fault, e.g. fault tolerance
    • GPHYSICS
    • G06COMPUTING; CALCULATING; COUNTING
    • G06FELECTRICAL DIGITAL DATA PROCESSING
    • G06F12/00Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02Addressing or allocation; Relocation
    • GPHYSICS
    • G06COMPUTING; CALCULATING; COUNTING
    • G06FELECTRICAL DIGITAL DATA PROCESSING
    • G06F1/00Details of data-processing equipment not covered by groups G06F3/00 - G06F13/00, e.g. cooling, packaging or power supply specially adapted for computer application

Similar Documents

Publication Publication Date Title
US8832413B2 (en) Processing system with interspersed processors and communication elements having improved wormhole routing
US5815723A (en) Picket autonomy on a SIMD machine
US5828894A (en) Array processor having grouping of SIMD pickets
US7673118B2 (en) System and method for vector-parallel multiprocessor communication
CN107590085B (en) A kind of dynamic reconfigurable array data path and its control method with multi-level buffer
EP0112885B1 (en) Interconnecting plane for modular array processor
JP2008537268A (en) An array of data processing elements with variable precision interconnection
US5765015A (en) Slide network for an array processor
CN113986813A (en) Method, system, device and storage medium for constructing and using network-on-chip structure
Baklouti et al. Study and integration of a parametric neighbouring interconnection network in a massively parallel architecture on FPGA
Tchuente Parallel Computation on regular arrays
CN112486905B (en) Reconfigurable isomerised PEA interconnection method
Soto et al. A self-adaptive hardware architecture with fault tolerance capabilities
Denholm et al. A unified approach for managing heterogeneous processing elements on FPGAs
EP0570952A2 (en) Slide network for an array processor
RU2397538C1 (en) Multiprocessor module
Krichene et al. SCAC-Net: Reconfigurable Interconnection Network in SCAC Massively parallel SoC
Baklouti et al. Reconfigurable communication networks in a parametric SIMD parallel system on chip
Kato et al. Evaluation of MuCCRA-D: A Dynamically Reconfigurable Processor with Directly Interconnected PEs.
Ferreira et al. Reducing interconnection cost in coarse-grained dynamic computing through multistage network
Puttegowda Context switching strategies in a run-time reconfigurable system
Bajwa et al. A Massively Parallel, Micro-grained VLSI Architecture
RU2282236C1 (en) Module for multi-processor system
Duvvuri Design, Development, and Simulation/Experimental Validation of a Crossbar Interconnection Network for a Single–Chip Shared Memory Multiprocessor Architecture
Kato et al. A study on interconnection networks of the Dynamically Reconfigurable Processor Array MuCCRA