Islam et al., 2009 - Google Patents
Design and Development of Clocked Transmission Gate Cross-Coupled Adiabatic CircuitIslam et al., 2009
View PDF- Document ID
- 17656262524329357446
- Author
- Islam A
- Hasan M
- Publication year
- Publication venue
- 2009 International Conference on Advances in Computing, Control, and Telecommunication Technologies
External Links
Snippet
In this paper, a novel clocked transmission gate cross-coupled adiabatic (CTGCA) circuit is proposed based on dual phase power clock generator. Unlike conventional power supply used in static CMOS logic, adiabatic logic requires AC-type supply voltage to recycle the …
- 230000005540 biological transmission 0 title abstract description 10
Classifications
-
- H—ELECTRICITY
- H03—BASIC ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K3/00—Circuits for generating electric pulses; Monostable, bistable or multistable circuits
- H03K3/02—Generators characterised by the type of circuit or by the means used for producing pulses
- H03K3/353—Generators characterised by the type of circuit or by the means used for producing pulses by the use, as active elements, of field-effect transistors with internal or external positive feedback
- H03K3/356—Bistable circuits
- H03K3/356104—Bistable circuits using complementary field-effect transistors
-
- H—ELECTRICITY
- H03—BASIC ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
- H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
- H03K19/08—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices
- H03K19/094—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices using field-effect transistors
- H03K19/096—Synchronous circuits, i.e. using clock signals
-
- H—ELECTRICITY
- H03—BASIC ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K3/00—Circuits for generating electric pulses; Monostable, bistable or multistable circuits
- H03K3/02—Generators characterised by the type of circuit or by the means used for producing pulses
- H03K3/027—Generators characterised by the type of circuit or by the means used for producing pulses by the use of logic circuits, with internal or external positive feedback
- H03K3/037—Bistable circuits
-
- H—ELECTRICITY
- H03—BASIC ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K5/00—Manipulating pulses not covered by one of the other main groups in this subclass
- H03K5/15—Arrangements in which pulses are delivered at different times at several outputs, i.e. pulse distributors
- H03K5/15013—Arrangements in which pulses are delivered at different times at several outputs, i.e. pulse distributors with more than two outputs
- H03K5/1506—Arrangements in which pulses are delivered at different times at several outputs, i.e. pulse distributors with more than two outputs with parallel driven output stages; with synchronously driven series connected output stages
- H03K5/15093—Arrangements in which pulses are delivered at different times at several outputs, i.e. pulse distributors with more than two outputs with parallel driven output stages; with synchronously driven series connected output stages using devices arranged in a shift register
-
- H—ELECTRICITY
- H03—BASIC ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K3/00—Circuits for generating electric pulses; Monostable, bistable or multistable circuits
- H03K3/01—Details
- H03K3/012—Modifications of generator to improve response time or to decrease power consumption
-
- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
- H02M3/00—Conversion of dc power input into dc power output
- H02M3/02—Conversion of dc power input into dc power output without intermediate conversion into ac
- H02M3/04—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters
- H02M3/06—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using resistors or capacitors, e.g. potential divider
- H02M3/07—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using resistors or capacitors, e.g. potential divider using capacitors charged and discharged alternately by semiconductor devices with control electrode, e.g. charge pumps
-
- H—ELECTRICITY
- H03—BASIC ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
- H03K19/01—Modifications for accelerating switching
- H03K19/017—Modifications for accelerating switching in field-effect transistor circuits
-
- H—ELECTRICITY
- H03—BASIC ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K23/00—Pulse counters comprising counting chains; Frequency dividers comprising counting chains
- H03K23/40—Gating or clocking signals applied to all stages, i.e. synchronous counters
-
- H—ELECTRICITY
- H03—BASIC ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K17/00—Electronic switching or gating, i.e. not by contact-making or -braking
- H03K17/51—Electronic switching or gating, i.e. not by contact-making or -braking characterised by the components used
-
- H—ELECTRICITY
- H03—BASIC ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K5/00—Manipulating pulses not covered by one of the other main groups in this subclass
- H03K2005/00013—Delay, i.e. output pulse is delayed after input pulse and pulse length of output pulse is dependent on pulse length of input pulse
- H03K2005/00019—Variable delay
-
- H—ELECTRICITY
- H03—BASIC ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
- H03K19/003—Modifications for increasing the reliability for protection
Similar Documents
Publication | Publication Date | Title |
---|---|---|
Maksimovic et al. | Clocked CMOS adiabatic logic with integrated single-phase power-clock supply | |
Lim et al. | A 16-bit carry-lookahead adder using reversible energy recovery logic for ultra-low-energy systems | |
JP3313276B2 (en) | MOS gate circuit and power supply method thereof | |
Lim et al. | nMOS reversible energy recovery logic for ultra-low-energy applications | |
Shinghal et al. | Adiabatic logic circuits: a retrospect | |
US5841299A (en) | Method and apparatus for implementing an adiabatic logic family | |
US5986476A (en) | Method and apparatus for implementing a dynamic adiabatic logic family | |
US5517145A (en) | CMOS toggle flip-flop using adiabatic switching | |
Reddy et al. | Cascadable adiabatic logic circuits for low-power applications | |
Chaudhuri et al. | Implementation of circuit in different adiabatic logic | |
Starosel'skii | Adiabatic logic circuits: A review | |
Hu et al. | Low-power adiabatic sequential circuits with complementary pass-transistor logic | |
Yadav et al. | Four phase clocking rule for energy efficient digital circuits—An adiabatic concept | |
Li et al. | Clocked CMOS adiabatic logic with low-power dissipation | |
Patel et al. | Comparative analysis of adiabatic logic techniques | |
Takahashi et al. | Two-phase clocked CMOS adiabatic logic | |
Maheshwari et al. | Impact of adiabatic logic families on the power-clock generator energy efficiency | |
Islam et al. | Design and Development of Clocked Transmission Gate Cross-Coupled Adiabatic Circuit | |
Puri et al. | A novel DFAL based frequency divider | |
Bhattacharjee et al. | A Low Power Adiabatic Approach for Scaled VLSI Circuits | |
Anuar et al. | Adiabatic logic versus CMOS for low power applications | |
Chanda et al. | Ultra low-power sequential circuit implementation by a Quasi-Static Single phase Adiabatic Dynamic Logic (SPADL) | |
Liu et al. | Improved structure for efficient charge recovery logic | |
Jain et al. | Sinusoidal power clock based PFAL | |
Chang et al. | Complementary pass-transistor energy recovery logic for low-power applications |