Wang et al., 2009 - Google Patents
A novel architecture for on-chip path delay measurementWang et al., 2009
View PDF- Document ID
- 1693826628019918177
- Author
- Wang X
- Tehranipoor M
- Datta R
- Publication year
- Publication venue
- 2009 International Test Conference
External Links
Snippet
As technology scales to 45nm and below, the deviation between predicted path delay using simulation and actual path delay on a manufactured chip increases. Hence, on-chip measurement architectures are now widely used due to their higher accuracy and lower cost …
- 238000005259 measurement 0 title abstract description 41
Classifications
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- G01R31/317—Testing of digital circuits
- G01R31/3181—Functional testing
- G01R31/3185—Reconfiguring for testing, e.g. LSSD, partitioning
- G01R31/318533—Reconfiguring for testing, e.g. LSSD, partitioning using scanning techniques, e.g. LSSD, Boundary Scan, JTAG
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- G01R31/318533—Reconfiguring for testing, e.g. LSSD, partitioning using scanning techniques, e.g. LSSD, Boundary Scan, JTAG
- G01R31/318536—Scan chain arrangements, e.g. connections, test bus, analog signals
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