[go: up one dir, main page]
More Web Proxy on the site http://driver.im/

Baglietto et al., 1995 - Google Patents

Parallel implementation of the full search block matching algorithm for motion estimation

Baglietto et al., 1995

View PDF
Document ID
16942861861320334670
Author
Baglietto P
Maresca M
Migliaro A
Migliardi M
Publication year
Publication venue
Proceedings The International Conference on Application Specific Array Processors

External Links

Snippet

Motion estimation is a key technique in most algorithms for video compression and particularly in the MPEG and H. 261 standards. The most frequently used technique is based on a Full Search Block Matching Algorithm which is highly computing intensive and requires …
Continue reading at www.researchgate.net (PDF) (other versions)

Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N5/00—Details of television systems
    • H04N5/14—Picture signal circuitry for video frequency region
    • H04N5/144—Movement detection
    • H04N5/145—Movement estimation
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N19/00—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals
    • H04N19/50—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals using predictive coding
    • H04N19/503—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals using predictive coding involving temporal prediction
    • H04N19/51—Motion estimation or motion compensation
    • H04N19/523—Motion estimation or motion compensation with sub-pixel accuracy
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N19/00—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals
    • H04N19/50—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals using predictive coding
    • H04N19/503—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals using predictive coding involving temporal prediction
    • H04N19/51—Motion estimation or motion compensation
    • H04N19/577—Motion compensation with bidirectional frame interpolation, i.e. using B-pictures
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N19/00—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals
    • H04N19/50—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals using predictive coding
    • H04N19/503—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals using predictive coding involving temporal prediction
    • H04N19/51—Motion estimation or motion compensation
    • H04N19/56—Motion estimation with initialisation of the vector search, e.g. estimating a good candidate to initiate a search
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N19/00—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals
    • H04N19/42—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals characterised by implementation details or hardware specially adapted for video compression or decompression, e.g. dedicated software implementation
    • H04N19/43—Hardware specially adapted for motion estimation or compensation
    • H04N19/433—Hardware specially adapted for motion estimation or compensation characterised by techniques for memory access
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N19/00—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals
    • H04N19/60—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals using transform coding
    • H04N19/61—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals using transform coding in combination with predictive coding
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING; COUNTING
    • G06T—IMAGE DATA PROCESSING OR GENERATION, IN GENERAL
    • G06T3/00—Geometric image transformation in the plane of the image, e.g. from bit-mapped to bit-mapped creating a different image
    • G06T3/40—Scaling the whole image or part thereof
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING; COUNTING
    • G06F—ELECTRICAL DIGITAL DATA PROCESSING
    • G06F17/00—Digital computing or data processing equipment or methods, specially adapted for specific functions
    • G06F17/10—Complex mathematical operations
    • G06F17/14—Fourier, Walsh or analogous domain transformations, e.g. Laplace, Hilbert, Karhunen-Loeve, transforms
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING; COUNTING
    • G06F—ELECTRICAL DIGITAL DATA PROCESSING
    • G06F15/00—Digital computers in general; Data processing equipment in general
    • G06F15/76—Architectures of general purpose stored programme computers
    • G06F15/80—Architectures of general purpose stored programme computers comprising an array of processing units with common control, e.g. single instruction multiple data processors
    • G06F15/8007—Architectures of general purpose stored programme computers comprising an array of processing units with common control, e.g. single instruction multiple data processors single instruction multiple data [SIMD] multiprocessors

Similar Documents

Publication Publication Date Title
US4937666A (en) Circuit implementation of block matching algorithm with fractional precision
US5719642A (en) Full-search block matching motion estimation processor
Yang et al. A family of VLSI designs for the motion compensation block-matching algorithm
US5696836A (en) Motion estimation processor architecture for full search block matching
US7020201B2 (en) Method and apparatus for motion estimation with all binary representation
EP0626791B1 (en) Motion vector detection apparatus for moving pictures
KR100486249B1 (en) Motion estimation apparatus and method for scanning a reference macroblock window in a search area
Lai et al. A data-interlacing architecture with two-dimensional data-reuse for full-search block-matching algorithm
US20070071101A1 (en) Systolic-array based systems and methods for performing block matching in motion compensation
KR101578052B1 (en) Motion estimation device and Moving image encoding device having the same
EP1120747A2 (en) Motion estimator
Baglietto et al. Parallel implementation of the full search block matching algorithm for motion estimation
KR100416444B1 (en) Motion vector selection method and image processing device performing this method
US20030012281A1 (en) Motion estimation apparatus and method for scanning an reference macroblock window in a search area
Yeh et al. Cost-effective VLSI architectures and buffer size optimization for full-search block matching algorithms
Baek et al. A fast array architecture for block matching algorithm
Yeo et al. A modular high-throughput architecture for logarithmic search block-matching motion estimation
Chen A cost-effective three-step hierarchical search block-matching chip for motion estimation
US20040047422A1 (en) Motion estimation using logarithmic search
Pirsch et al. VLSI architectures for block matching algorithms
KR0178302B1 (en) Motion estimation processor based on the bidirectional parallel pipe line structure
US6968011B2 (en) Motion vector detecting device improved in detection speed of motion vectors and system employing the same devices
EP1086591A1 (en) Motion estimation
Wehberg et al. Architecture of a programmable real-time processor for digital video signals adapted to motion estimation algorithms
Schmidt et al. A parallel accelerator architecture for multimedia video compression