Datta et al., 2010 - Google Patents
Calibration of on-chip thermal sensors using process monitoring circuitsDatta et al., 2010
- Document ID
- 16744573292157830406
- Author
- Datta B
- Burleson W
- Publication year
- Publication venue
- 2010 11th international symposium on quality electronic design (ISQED)
External Links
Snippet
Remarkable increase in peak power-density values coupled with the hotspot migration caused by workload variance motivates the need for multiple thermal monitoring circuits distributed across the die. The effect of intra-die process-variations on deep sub-micron …
- 238000000034 method 0 title abstract description 34
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING; COUNTING
- G06F—ELECTRICAL DIGITAL DATA PROCESSING
- G06F17/00—Digital computing or data processing equipment or methods, specially adapted for specific functions
- G06F17/50—Computer-aided design
- G06F17/5009—Computer-aided design using simulation
- G06F17/5036—Computer-aided design using simulation for analog modelling, e.g. for circuits, spice programme, direct methods, relaxation methods
-
- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/30—Marginal testing, e.g. varying supply voltage
- G01R31/3004—Current or voltage test
-
- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/2851—Testing of integrated circuits [IC]
-
- G—PHYSICS
- G05—CONTROLLING; REGULATING
- G05F—SYSTEMS FOR REGULATING ELECTRIC OR MAGNETIC VARIABLES
- G05F3/00—Non-retroactive systems for regulating electric variables by using an uncontrolled element, or an uncontrolled combination of elements, such element or such combination having self-regulating properties
- G05F3/02—Regulating voltage or current
- G05F3/08—Regulating voltage or current wherein the variable is dc
- G05F3/10—Regulating voltage or current wherein the variable is dc using uncontrolled devices with non-linear characteristics
- G05F3/16—Regulating voltage or current wherein the variable is dc using uncontrolled devices with non-linear characteristics being semiconductor devices
-
- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/26—Testing of individual semiconductor devices
- G01R31/2642—Testing semiconductor operation lifetime or reliability, e.g. by accelerated life tests
-
- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/317—Testing of digital circuits
- G01R31/3181—Functional testing
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING; COUNTING
- G06F—ELECTRICAL DIGITAL DATA PROCESSING
- G06F2217/00—Indexing scheme relating to computer aided design [CAD]
- G06F2217/78—Power analysis and optimization
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING; COUNTING
- G06F—ELECTRICAL DIGITAL DATA PROCESSING
- G06F2217/00—Indexing scheme relating to computer aided design [CAD]
- G06F2217/70—Fault tolerant, i.e. transient fault suppression
Similar Documents
Publication | Publication Date | Title |
---|---|---|
US8154353B2 (en) | Operating parameter monitor for an integrated circuit | |
Singh et al. | Dynamic nbti management using a 45 nm multi-degradation sensor | |
Islam et al. | Wide-supply-range all-digital leakage variation sensor for on-chip process and temperature monitoring | |
Shah et al. | On-chip adaptive body bias for reducing the impact of NBTI on 6T SRAM cells | |
US7868606B2 (en) | Process variation on-chip sensor | |
Cabe et al. | Small embeddable NBTI sensors (SENS) for tracking on-chip performance decay | |
Rossi et al. | Reliable power gating with NBTI aging benefits | |
An et al. | All-digital on-chip process sensor using ratioed inverter-based ring oscillator | |
Karimi et al. | A low area overhead NBTI/PBTI sensor for SRAM memories | |
Mangalagiri et al. | Thermal-aware reliability analysis for platform FPGAs | |
Datta et al. | Calibration of on-chip thermal sensors using process monitoring circuits | |
Islam et al. | Statistical analysis and modeling of random telegraph noise based on gate delay measurement | |
McAndrew et al. | Extensions to backward propagation of variance for statistical modeling | |
Mottaghi et al. | Aging mitigation in FPGAs considering delay, power, and temperature | |
Abu-Rahma et al. | Variability in nanometer technologies and impact on SRAM | |
Laurenciu et al. | A direct measurement scheme of amalgamated aging effects with novel on-chip sensor | |
Zhang et al. | Impact of front-end wearout mechanisms on the performance of a ring oscillator-based thermal sensor | |
Calimera et al. | Power-gating for leakage control and beyond | |
Deng et al. | SOI FinFET nFET-to-pFET tracking variability compact modeling and impact on latch timing | |
Fuketa et al. | Transistor variability modeling and its validation with ring-oscillation frequencies for body-biased subthreshold circuits | |
Datta et al. | Low-power, process-variation tolerant on-chip thermal monitoring using track and hold based thermal sensors | |
Banerjee et al. | Leakage and variation aware thermal management of nanometer scale ICs | |
Datta et al. | A 45.6 μ2 13.4 μw 7.1 v/v resolution sub-threshold based digital process-sensing circuit in 45nm CMOS | |
Tenentes et al. | Leakage current analysis for diagnosis of bridge defects in power-gating designs | |
Datta et al. | A 45.6 µ2 13.4 µW 7.1 V/V Resolution Sub-Threshold Based Digital Process-Sensing Circuit in 45nm CMOS |