[go: up one dir, main page]
More Web Proxy on the site http://driver.im/

Tseng et al., 1999 - Google Patents

A gridless multilayer router for standard cell circuits using CTM cells

Tseng et al., 1999

View PDF
Document ID
16622252016795599595
Author
Tseng H
Sechen C
Publication year
Publication venue
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

External Links

Snippet

We present a gridless multilayer router suitable for standard cell circuits using central terminal model (CTM) cells. A CTM cell has pins in the middle which split the over-the-cell (OTC) routing region into top and bottom parts. Nets are routed in both the channel (if …
Continue reading at www.researchgate.net (PDF) (other versions)

Classifications

    • GPHYSICS
    • G06COMPUTING; CALCULATING; COUNTING
    • G06FELECTRICAL DIGITAL DATA PROCESSING
    • G06F17/00Digital computing or data processing equipment or methods, specially adapted for specific functions
    • G06F17/50Computer-aided design
    • G06F17/5068Physical circuit design, e.g. layout for integrated circuits or printed circuit boards
    • G06F17/5077Routing
    • GPHYSICS
    • G06COMPUTING; CALCULATING; COUNTING
    • G06FELECTRICAL DIGITAL DATA PROCESSING
    • G06F17/00Digital computing or data processing equipment or methods, specially adapted for specific functions
    • G06F17/50Computer-aided design
    • G06F17/5068Physical circuit design, e.g. layout for integrated circuits or printed circuit boards
    • G06F17/5081Layout analysis, e.g. layout verification, design rule check
    • GPHYSICS
    • G06COMPUTING; CALCULATING; COUNTING
    • G06FELECTRICAL DIGITAL DATA PROCESSING
    • G06F17/00Digital computing or data processing equipment or methods, specially adapted for specific functions
    • G06F17/50Computer-aided design
    • G06F17/5068Physical circuit design, e.g. layout for integrated circuits or printed circuit boards
    • G06F17/5072Floorplanning, e.g. partitioning, placement
    • GPHYSICS
    • G06COMPUTING; CALCULATING; COUNTING
    • G06FELECTRICAL DIGITAL DATA PROCESSING
    • G06F17/00Digital computing or data processing equipment or methods, specially adapted for specific functions
    • G06F17/50Computer-aided design
    • G06F17/5045Circuit design
    • G06F17/505Logic synthesis, e.g. technology mapping, optimisation
    • GPHYSICS
    • G06COMPUTING; CALCULATING; COUNTING
    • G06FELECTRICAL DIGITAL DATA PROCESSING
    • G06F17/00Digital computing or data processing equipment or methods, specially adapted for specific functions
    • G06F17/30Information retrieval; Database structures therefor; File system structures therefor
    • G06F17/30943Information retrieval; Database structures therefor; File system structures therefor details of database functions independent of the retrieved data type
    • G06F17/30946Information retrieval; Database structures therefor; File system structures therefor details of database functions independent of the retrieved data type indexing structures
    • G06F17/30961Trees
    • GPHYSICS
    • G06COMPUTING; CALCULATING; COUNTING
    • G06FELECTRICAL DIGITAL DATA PROCESSING
    • G06F17/00Digital computing or data processing equipment or methods, specially adapted for specific functions
    • G06F17/50Computer-aided design
    • G06F17/5009Computer-aided design using simulation

Similar Documents

Publication Publication Date Title
Tseng et al. A gridless multilayer router for standard cell circuits using CTM cells
US5856927A (en) Method for automatically routing circuits of very large scale integration (VLSI)
US7065730B2 (en) Porosity aware buffered steiner tree construction
Kahng et al. On optimal interconnections for VLSI
US6247167B1 (en) Method and apparatus for parallel Steiner tree routing
US6324674B2 (en) Method and apparatus for parallel simultaneous global and detail routing
US6154874A (en) Memory-saving method and apparatus for partitioning high fanout nets
Guruswamy et al. CELLERITY: A fully automatic layout synthesis system for standard cell libraries
Cong et al. Matching-based methods for high-performance clock routing
Cong et al. An implicit connection graph maze routing algorithm for ECO routing
US6260183B1 (en) Method and apparatus for coarse global routing
Cong et al. An enhanced multilevel routing system
Cho et al. Four-bend top-down global routing
Chen et al. Refined single trunk tree: A rectilinear Steiner tree generator for interconnect prediction
Alpert et al. Steiner tree optimization for buffers, blockages, and bays
Igusa et al. ORCA A sea-of-gates place and route system
Li et al. An efficient tile-based ECO router with routing graph reduction and enhanced global routing flow
Liu et al. Chip-level area routing
Kao et al. Cross point assignment with global rerouting for general-architecture designs
Lee et al. A global router for sea-of-gates circuits
Katsadas et al. A multi-layer router utilizing over-cell areas
Mehta et al. On the use of flexible, rectilinear blocks to obtain minimum-area floorplans in mixed block and cell designs
Chen et al. A new global router for ASIC design based on simulated evolution
US6477692B1 (en) Method and apparatus for channel-routing of an electronic device
Dayan Rubber-band based topological router