[go: up one dir, main page]
More Web Proxy on the site http://driver.im/

Sill et al., 2007 - Google Patents

Design of mixed gates for leakage reduction

Sill et al., 2007

View PDF
Document ID
16685312138254802466
Author
Sill F
You J
Timmermann D
Publication year
Publication venue
Proceedings of the 17th ACM Great Lakes symposium on VLSI

External Links

Snippet

Leakage power dissipation is one of the most critical factors for the overall current dissipation and future designs. However, design techniques for the reduction of leakage power should not decrease design performance. Therefore, an enhanced Dual Vth/Dual Tox …
Continue reading at www.amd.e-technik.uni-rostock.de (PDF) (other versions)

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING; COUNTING
    • G06F—ELECTRICAL DIGITAL DATA PROCESSING
    • G06F17/00—Digital computing or data processing equipment or methods, specially adapted for specific functions
    • G06F17/50—Computer-aided design
    • G06F17/5009—Computer-aided design using simulation
    • G06F17/5036—Computer-aided design using simulation for analog modelling, e.g. for circuits, spice programme, direct methods, relaxation methods
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING; COUNTING
    • G06F—ELECTRICAL DIGITAL DATA PROCESSING
    • G06F17/00—Digital computing or data processing equipment or methods, specially adapted for specific functions
    • G06F17/50—Computer-aided design
    • G06F17/5009—Computer-aided design using simulation
    • G06F17/5022—Logic simulation, e.g. for logic circuit operation
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING; COUNTING
    • G06F—ELECTRICAL DIGITAL DATA PROCESSING
    • G06F17/00—Digital computing or data processing equipment or methods, specially adapted for specific functions
    • G06F17/50—Computer-aided design
    • G06F17/5045—Circuit design
    • G06F17/505—Logic synthesis, e.g. technology mapping, optimisation
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING; COUNTING
    • G06F—ELECTRICAL DIGITAL DATA PROCESSING
    • G06F17/00—Digital computing or data processing equipment or methods, specially adapted for specific functions
    • G06F17/50—Computer-aided design
    • G06F17/5068—Physical circuit design, e.g. layout for integrated circuits or printed circuit boards
    • G06F17/5081—Layout analysis, e.g. layout verification, design rule check
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING; COUNTING
    • G06F—ELECTRICAL DIGITAL DATA PROCESSING
    • G06F2217/00—Indexing scheme relating to computer aided design [CAD]
    • G06F2217/78—Power analysis and optimization
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING; COUNTING
    • G06F—ELECTRICAL DIGITAL DATA PROCESSING
    • G06F1/00—Details of data-processing equipment not covered by groups G06F3/00 - G06F13/00, e.g. cooling, packaging or power supply specially adapted for computer application
    • G06F1/26—Power supply means, e.g. regulation thereof
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING; COUNTING
    • G06F—ELECTRICAL DIGITAL DATA PROCESSING
    • G06F1/00—Details of data-processing equipment not covered by groups G06F3/00 - G06F13/00, e.g. cooling, packaging or power supply specially adapted for computer application
    • G06F1/16—Constructional details or arrangements
    • H—ELECTRICITY
    • H03—BASIC ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/0008—Arrangements for reducing power consumption
    • H03K19/0016—Arrangements for reducing power consumption by using a control or a clock signal, e.g. in order to apply power supply
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING; COUNTING
    • G06F—ELECTRICAL DIGITAL DATA PROCESSING
    • G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
    • H—ELECTRICITY
    • H03—BASIC ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/003—Modifications for increasing the reliability for protection
    • H—ELECTRICITY
    • H03—BASIC ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components

Similar Documents

Publication Publication Date Title
Wei et al. Mixed-Vth (MVT) CMOS circuit design methodology for low power applications
Tsai et al. Implications of technology scaling on leakage reduction techniques
Quader et al. Hot-carrier-reliability design guidelines for CMOS logic circuits
Calimera et al. NBTI-aware clustered power gating
US9424381B2 (en) Contributor-based power modeling of microprocessor components
Sill et al. Design of mixed gates for leakage reduction
Calimera et al. Design of a flexible reactivation cell for safe power-mode transition in power-gated circuits
Dhanwada et al. Leakage power contributor modeling
Ko et al. Short-circuit power driven gate sizing technique for reducing power dissipation
Sharma et al. Effective drive current for near-threshold CMOS circuits’ performance evaluation: Modeling to circuit design techniques
da Silva et al. CMOS logic gate performance variability related to transistor network arrangements
Zarei et al. Modeling symmetrical independent gate FinFET using predictive technology model
Monteiro et al. Power analysis and optimization from circuit to register-transfer levels
Vaidyanathan et al. Improving energy efficiency of low-voltage logic by technology-driven design
Sill et al. Low power gate-level design with mixed-Vth (MVT) techniques
Sill et al. Total leakage power optimization with improved Mixed Gates
Nesset Rtl power estimation flow and its use in power optimization
Chentouf et al. Power-aware hold optimization for ASIC physical synthesis
Sill et al. Reducing leakage with mixed-V/sub th/(MVT)
Jooypa et al. Statistical Strategies to Capture Correlation Between Overshooting Effect and Propagation Delay Time in Nano-CMOS Inverters
Anderson Power optimization and prediction techniques for FPGAs
Fu Cost-performance optimizations of microprocessors
Mendoza et al. CMOS leakage power at cell level
Goyal Characterizing processors for time and energy optimization
Chou Computationally efficient characterization of standard cells for statistical static timing analysis