Ismail, 2002 - Google Patents
Evaluation of dynamic branch predictors for modern ILP processorsIsmail, 2002
View PDF- Document ID
- 16405706741544218297
- Author
- Ismail N
- Publication year
- Publication venue
- Microprocessors and Microsystems
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Snippet
Modern instruction-level parallel (ILP) processors use superscalar architectures with deep pipelines in order to execute multiple instructions per cycle. The frequency and behavior of branch instructions seriously hinder performance of ILP processors. Various mechanisms …
- 238000011156 evaluation 0 title description 4
Classifications
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- G06F9/3836—Instruction issuing, e.g. dynamic instruction scheduling, out of order instruction execution
- G06F9/3842—Speculative instruction execution
- G06F9/3844—Speculative instruction execution using dynamic prediction, e.g. branch history table
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