[go: up one dir, main page]
More Web Proxy on the site http://driver.im/

Hu et al., 2000 - Google Patents

A timing-constrained algorithm for simultaneous global routing of multiple nets

Hu et al., 2000

View PDF
Document ID
16241072479759486935
Author
Hu J
Sapatnekar S
Publication year
Publication venue
IEEE/ACM International Conference on Computer Aided Design. ICCAD-2000. IEEE/ACM Digest of Technical Papers (Cat. No. 00CH37140)

External Links

Snippet

In this paper we propose a new approach for VLSI interconnect global routing that can optimize both congestion and delay, which are often competing objectives. Our approach provides a general framework that may use any single-net routing algorithm and any delay …
Continue reading at www.ece.umn.edu (PDF) (other versions)

Classifications

    • GPHYSICS
    • G06COMPUTING; CALCULATING; COUNTING
    • G06FELECTRICAL DIGITAL DATA PROCESSING
    • G06F17/00Digital computing or data processing equipment or methods, specially adapted for specific functions
    • G06F17/50Computer-aided design
    • G06F17/5068Physical circuit design, e.g. layout for integrated circuits or printed circuit boards
    • G06F17/5077Routing
    • GPHYSICS
    • G06COMPUTING; CALCULATING; COUNTING
    • G06FELECTRICAL DIGITAL DATA PROCESSING
    • G06F17/00Digital computing or data processing equipment or methods, specially adapted for specific functions
    • G06F17/50Computer-aided design
    • G06F17/5068Physical circuit design, e.g. layout for integrated circuits or printed circuit boards
    • G06F17/5072Floorplanning, e.g. partitioning, placement
    • GPHYSICS
    • G06COMPUTING; CALCULATING; COUNTING
    • G06FELECTRICAL DIGITAL DATA PROCESSING
    • G06F17/00Digital computing or data processing equipment or methods, specially adapted for specific functions
    • G06F17/50Computer-aided design
    • G06F17/5045Circuit design
    • G06F17/505Logic synthesis, e.g. technology mapping, optimisation
    • GPHYSICS
    • G06COMPUTING; CALCULATING; COUNTING
    • G06FELECTRICAL DIGITAL DATA PROCESSING
    • G06F17/00Digital computing or data processing equipment or methods, specially adapted for specific functions
    • G06F17/50Computer-aided design
    • G06F17/5068Physical circuit design, e.g. layout for integrated circuits or printed circuit boards
    • G06F17/5081Layout analysis, e.g. layout verification, design rule check
    • GPHYSICS
    • G06COMPUTING; CALCULATING; COUNTING
    • G06FELECTRICAL DIGITAL DATA PROCESSING
    • G06F17/00Digital computing or data processing equipment or methods, specially adapted for specific functions
    • G06F17/50Computer-aided design
    • G06F17/5009Computer-aided design using simulation
    • GPHYSICS
    • G06COMPUTING; CALCULATING; COUNTING
    • G06FELECTRICAL DIGITAL DATA PROCESSING
    • G06F17/00Digital computing or data processing equipment or methods, specially adapted for specific functions
    • G06F17/30Information retrieval; Database structures therefor; File system structures therefor
    • GPHYSICS
    • G06COMPUTING; CALCULATING; COUNTING
    • G06FELECTRICAL DIGITAL DATA PROCESSING
    • G06F2217/00Indexing scheme relating to computer aided design [CAD]
    • G06F2217/12Design for manufacturability
    • GPHYSICS
    • G06COMPUTING; CALCULATING; COUNTING
    • G06QDATA PROCESSING SYSTEMS OR METHODS, SPECIALLY ADAPTED FOR ADMINISTRATIVE, COMMERCIAL, FINANCIAL, MANAGERIAL, SUPERVISORY OR FORECASTING PURPOSES; SYSTEMS OR METHODS SPECIALLY ADAPTED FOR ADMINISTRATIVE, COMMERCIAL, FINANCIAL, MANAGERIAL, SUPERVISORY OR FORECASTING PURPOSES, NOT OTHERWISE PROVIDED FOR
    • G06Q10/00Administration; Management
    • G06Q10/04Forecasting or optimisation, e.g. linear programming, "travelling salesman problem" or "cutting stock problem"
    • GPHYSICS
    • G06COMPUTING; CALCULATING; COUNTING
    • G06FELECTRICAL DIGITAL DATA PROCESSING
    • G06F2217/00Indexing scheme relating to computer aided design [CAD]
    • G06F2217/78Power analysis and optimization
    • GPHYSICS
    • G06COMPUTING; CALCULATING; COUNTING
    • G06FELECTRICAL DIGITAL DATA PROCESSING
    • G06F2217/00Indexing scheme relating to computer aided design [CAD]
    • G06F2217/08Multi-objective optimization

Similar Documents

Publication Publication Date Title
Hu et al. A timing-constrained algorithm for simultaneous global routing of multiple nets
US7137097B1 (en) Constraint-based global router for routing high performance designs
Cong et al. DUNE: A multi-layer gridless routing system with wire planning
US6415427B2 (en) Method and apparatus for global routing, and storage medium having global routing program stored therein
US6543043B1 (en) Inter-region constraint-based router for use in electronic design automation
US6480991B1 (en) Timing-driven global placement based on geometry-aware timing budgets
Cong et al. Buffer block planning for interconnect-driven floorplanning
US7661085B2 (en) Method and system for performing global routing on an integrated circuit design
US6442745B1 (en) Method and apparatus for layout-constrained global routing
US8015522B2 (en) System for implementing post-silicon IC design changes
US9552454B2 (en) Concurrent timing-driven topology construction and buffering for VLSI routing
US7707536B2 (en) V-shaped multilevel full-chip gridless routing
Shen et al. Efficient rectilinear Steiner tree construction with rectilinear blockages
US7290239B1 (en) Method and apparatus for performing post-placement functional decomposition for field programmable gate arrays
Hu et al. A timing-constrained simultaneous global routing algorithm
US5701255A (en) Cell generation method and cell generation system
Xu et al. Cluster refinement for block placement
US6615401B1 (en) Blocked net buffer insertion
Wang et al. Performance-driven interconnect global routing
Behjat et al. Integer linear programming models for global routing
US9213794B2 (en) System and method for routing buffered interconnects in an integrated circuit
Rafiq et al. Bus-based integrated floorplanning
US11461529B1 (en) Routing with soft-penalizing pixels on a found path
Monteiro et al. An optimized cost flow algorithm to spread cells in detailed placement
Shi et al. Macro block based FPGA floorplanning