[go: up one dir, main page]
More Web Proxy on the site http://driver.im/

Palchaudhuri et al., 2020 - Google Patents

Testable architecture design for programmable cellular automata on FPGA using run-time dynamically reconfigurable look-up tables

Palchaudhuri et al., 2020

Document ID
16147691610341672549
Author
Palchaudhuri A
Dhar A
Publication year
Publication venue
Journal of Electronic Testing

External Links

Snippet

In this paper, we have achieved run-time dynamic reconfiguration by employing a category of logic cells equipped to realize programmability in Cellular Automata (CA) architectures on Field Programmable Gate Arrays (FPGAs). This is essential for real time VLSI …
Continue reading at link.springer.com (other versions)

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING; COUNTING
    • G06F—ELECTRICAL DIGITAL DATA PROCESSING
    • G06F17/00—Digital computing or data processing equipment or methods, specially adapted for specific functions
    • G06F17/50—Computer-aided design
    • G06F17/5045—Circuit design
    • G06F17/5054—Circuit design for user-programmable logic devices, e.g. field programmable gate arrays [FPGA]
    • H—ELECTRICITY
    • H03—BASIC ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
    • H03K19/173—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components
    • H03K19/177—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components arranged in matrix form
    • H03K19/17724—Structural details of logic blocks
    • H03K19/17728—Reconfigurable logic blocks, e.g. lookup tables
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317—Testing of digital circuits
    • G01R31/3181—Functional testing
    • G01R31/3185—Reconfiguring for testing, e.g. LSSD, partitioning
    • H—ELECTRICITY
    • H03—BASIC ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
    • H03K19/173—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components
    • H03K19/177—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components arranged in matrix form
    • H03K19/17736—Structural details of routing resources
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING; COUNTING
    • G06F—ELECTRICAL DIGITAL DATA PROCESSING
    • G06F17/00—Digital computing or data processing equipment or methods, specially adapted for specific functions
    • G06F17/50—Computer-aided design
    • G06F17/5009—Computer-aided design using simulation
    • H—ELECTRICITY
    • H03—BASIC ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
    • H03K19/173—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components
    • H03K19/1733—Controllable logic circuits
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING; COUNTING
    • G06F—ELECTRICAL DIGITAL DATA PROCESSING
    • G06F15/00—Digital computers in general; Data processing equipment in general
    • G06F15/76—Architectures of general purpose stored programme computers
    • G06F15/78—Architectures of general purpose stored programme computers comprising a single central processing unit
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING; COUNTING
    • G06F—ELECTRICAL DIGITAL DATA PROCESSING
    • G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING; COUNTING
    • G06F—ELECTRICAL DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring

Similar Documents

Publication Publication Date Title
US8324937B2 (en) Methods for differential pair conductor routing in a logic circuit
Huang et al. Testing configurable LUT-based FPGA's
JP5354427B2 (en) Reconfigurable logical fabric for integrated circuits and systems and methods for configuring a reconfigurable logical fabric
US8813013B2 (en) Partitioning designs to facilitate certification
US9032343B1 (en) Integrating multiple FPGA designs by merging configuration settings
US10855285B2 (en) Field programmable transistor arrays
Tian et al. A field programmable transistor array featuring single-cycle partial/full dynamic reconfiguration
Palchaudhuri et al. Speed-area optimized VLSI architecture of multi-bit cellular automaton cell based random number generator on FPGA with testable logic support
WO2011069057A1 (en) Preventing information leakage between components on a programmable chip in the presence of faults
Palchaudhuri et al. Design and automation of VLSI architectures for bidirectional scan based fault localization approach in FPGA fabric aware cellular automata topologies
Palchaudhuri et al. Testable architecture design for programmable cellular automata on FPGA using run-time dynamically reconfigurable look-up tables
US7725855B1 (en) Symmetry-based optimization for the physical synthesis of programmable logic devices
Glaser et al. Methodology and example-driven interconnect synthesis for designing heterogeneous coarse-grain reconfigurable architectures
Palchaudhuri et al. Efficient Automated Implementation of Testable Cellular Automata Based Pseudorandom Generator Circuits on FPGAs.
Parvez et al. Application-specific fpga using heterogeneous logic blocks
Girard et al. Delay fault testing of look-up tables in SRAM-based FPGAs
Banik et al. An integrated framework for application independent testing of fpga interconnect
Wu et al. Fault detection and location of dynamic reconfigurable FPGAs
Lantz A QCA implementation of a look-up table for an FPGA
Malhotra et al. A Novel Embryonic Cellular Architecture with BIST for Deep Space Systems
Qian et al. Two-level logic synthesis for probabilistic computation
Harris Built-In Self-Test Configurations for Field Programmable Gate Array Cores in Systems on Chip
EP2793149B1 (en) Partitioning designs to facilitate certification
Lodi et al. Compact buffered routing architecture
Newalkar Alternative Techniques for Built-In Self-Test of Field Programmable Gate Arrays