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Gu et al., 2001 - Google Patents

An effort-minimized logic BIST implementation method

Gu et al., 2001

View PDF
Document ID
16068352189906002531
Author
Gu X
Chung S
Tsang F
Tofte J
Rahmanian H
Publication year
Publication venue
Proceedings International Test Conference 2001 (Cat. No. 01CH37260)

External Links

Snippet

This paper presents LBIST (Logic Built-In Self Test) design practice at Cisco Systems. It focuses on the LBIST design tasks that could affect design schedules and efforts. These are design timing closure and signature mismatch debugging. Our timing closure technique …
Continue reading at www.academia.edu (PDF) (other versions)

Classifications

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    • G01R31/318566—Comparators; Diagnosing the device under test
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    • G—PHYSICS
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    • G01R31/3181—Functional testing
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    • G—PHYSICS
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    • G06F—ELECTRICAL DIGITAL DATA PROCESSING
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    • G—PHYSICS
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    • G06F11/00—Error detection; Error correction; Monitoring
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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
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    • G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
    • G11C29/12—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
    • G11C29/14—Implementation of control logic, e.g. test mode decoders

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