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Endrinal et al., 2024 - Google Patents

Solving Complex Electrical Fault Isolation Challenges with Innovative DFT Strategies

Endrinal et al., 2024

Document ID
15990523219114115552
Author
Endrinal L
Kinger R
Pradeep W
Mittal S
Saujauddin J
Ho S
Suri J
Chittora A
Kassab M
Orlando P
Publication year
Publication venue
International Symposium for Testing and Failure Analysis

External Links

Snippet

Abstract As System-on-a-Chip (SoC) continues to increase in complexity, multiple functionalities are being integrated into one integrated circuit (IC). This requires optimization of Design-for-Testability (DFT) strategies to minimize test time while still ensuring full test …
Continue reading at dl.asminternational.org (other versions)

Classifications

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    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/302—Contactless testing

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