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Hussain et al., 2012 - Google Patents

PPMC: a programmable pattern based memory controller

Hussain et al., 2012

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Document ID
1595195562364196084
Author
Hussain T
Shafiq M
Pericas M
Navarro N
Ayguadé E
Publication year
Publication venue
Reconfigurable Computing: Architectures, Tools and Applications: 8th International Symposium, ARC 2012, Hong Kong, China, March 19-23, 2012. Proceedings 8

External Links

Snippet

One of the main challenges in the design of hardware accelerators is the efficient access of data from the external memory. Improving and optimizing the functionality of the memory controller between the external memory and the accelerators is therefore critical. In this …
Continue reading at www.researchgate.net (PDF) (other versions)

Classifications

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    • G06F12/08Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0806Multiuser, multiprocessor or multiprocessing cache systems
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    • G06F9/3885Concurrent instruction execution, e.g. pipeline, look ahead using a plurality of independent parallel functional units
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    • G06F9/3891Concurrent instruction execution, e.g. pipeline, look ahead using a plurality of independent parallel functional units controlled by multiple instructions, e.g. MIMD, decoupled access or execute organised in groups of units sharing resources, e.g. clusters
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    • G06F13/161Handling requests for interconnection or transfer for access to memory bus based on arbitration with latency improvement
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