Bourdi et al., 2007 - Google Patents
CMOS Single Chip Fast Frequency Hopping Synthesizers for Wireless Multi-gigahertz Applications: Design Methodology, Analysis, and ImplementationBourdi et al., 2007
- Document ID
- 15945750103196330013
- Author
- Bourdi T
- Kale I
- Publication year
External Links
Snippet
Recently, wireless LAN standards have emerged in the market. Those standards operate in various frequency ranges. To reduce component count, it is of importance to design a multi- mode frequency synthesizer that serves all wireless LAN standards including 802.11 a …
- 238000000034 method 0 title abstract description 42
Classifications
-
- H—ELECTRICITY
- H03—BASIC ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION, OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/16—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop
- H03L7/18—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using a frequency divider or counter in the loop
- H03L7/197—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using a frequency divider or counter in the loop a time difference being used for locking the loop, the counter counting between numbers which are variable in time or the frequency divider dividing by a factor variable in time, e.g. for obtaining fractional frequency division
- H03L7/1974—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using a frequency divider or counter in the loop a time difference being used for locking the loop, the counter counting between numbers which are variable in time or the frequency divider dividing by a factor variable in time, e.g. for obtaining fractional frequency division for fractional frequency division
- H03L7/1976—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using a frequency divider or counter in the loop a time difference being used for locking the loop, the counter counting between numbers which are variable in time or the frequency divider dividing by a factor variable in time, e.g. for obtaining fractional frequency division for fractional frequency division using a phase accumulator for controlling the counter or frequency divider
-
- H—ELECTRICITY
- H03—BASIC ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION, OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/08—Details of the phase-locked loop
- H03L7/085—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal
- H03L7/093—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal using special filtering or amplification characteristics in the loop
-
- H—ELECTRICITY
- H03—BASIC ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION, OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/08—Details of the phase-locked loop
- H03L7/099—Details of the phase-locked loop concerning mainly the controlled oscillator of the loop
-
- H—ELECTRICITY
- H03—BASIC ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION, OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/08—Details of the phase-locked loop
- H03L7/085—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal
- H03L7/089—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal the phase or frequency detector generating up-down pulses
- H03L7/0891—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal the phase or frequency detector generating up-down pulses the up-down pulses controlling source and sink current generators, e.g. a charge pump
-
- H—ELECTRICITY
- H03—BASIC ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION, OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/08—Details of the phase-locked loop
- H03L7/10—Details of the phase-locked loop for assuring initial synchronisation or for broadening the capture range
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04B—TRANSMISSION
- H04B1/00—Details of transmission systems, not covered by a single one of groups H04B3/00 - H04B13/00; Details of transmission systems not characterised by the medium used for transmission
- H04B1/02—Transmitters
- H04B1/04—Circuits
-
- H—ELECTRICITY
- H03—BASIC ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION, OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L2207/00—Indexing scheme relating to automatic control of frequency or phase and to synchronisation
-
- H—ELECTRICITY
- H03—BASIC ELECTRONIC CIRCUITRY
- H03B—GENERATION OF OSCILLATIONS, DIRECTLY OR BY FREQUENCY-CHANGING, BY CIRCUITS EMPLOYING ACTIVE ELEMENTS WHICH OPERATE IN A NON-SWITCHING MANNER; GENERATION OF NOISE BY SUCH CIRCUITS
- H03B19/00—Generation of oscillations by non-regenerative frequency multiplication or division of a signal from a separate source
Similar Documents
Publication | Publication Date | Title |
---|---|---|
US7532679B2 (en) | Hybrid polar/cartesian digital modulator | |
US7365607B2 (en) | Low-power, low-jitter, fractional-N all-digital phase-locked loop (PLL) | |
Shu et al. | CMOS PLL synthesizers: analysis and design | |
Staszewski et al. | All-digital PLL and transmitter for mobile phones | |
Staszewski et al. | All-digital frequency synthesizer in deep-submicron CMOS | |
Vaucher | Architectures for RF frequency synthesizers | |
Marzin et al. | A 20 Mb/s phase modulator based on a 3.6 GHz digital PLL with− 36 dB EVM at 5 mW power | |
CN104836580B (en) | Arbitrary phase trajectory frequency synthesizer | |
Meninger et al. | A 1-MHZ bandwidth 3.6-GHz 0.18-/spl mu/m CMOS fractional-N synthesizer utilizing a hybrid PFD/DAC structure for reduced broadband phase noise | |
US7920081B2 (en) | Digital phase locked loop with dithering | |
US7570182B2 (en) | Adaptive spectral noise shaping to improve time to digital converter quantization resolution using dithering | |
Staszewski et al. | Spur-free multirate all-digital PLL for mobile phones in 65 nm CMOS | |
Lu et al. | A 3–10 GHz, 14 bands CMOS frequency synthesizer with spurs reduction for MB-OFDM UWB system | |
Xu et al. | A 2.4-GHz low-power all-digital phase-locked loop | |
Rogers et al. | A multiband/spl Delta//spl Sigma/fractional-N frequency synthesizer for a MIMO WLAN transceiver RFIC | |
Xu et al. | A 3.6 GHz low-noise fractional-N digital PLL using SAR-ADC-based TDC | |
US11411567B2 (en) | Phase interpolation-based fractional-N sampling phase-locked loop | |
Chien et al. | A 4GHz fractional-N synthesizer for IEEE 802.11 a | |
Zhang et al. | A hybrid spur compensation technique for finite-modulo fractional-N phase-locked loops | |
Bourdi et al. | CMOS Single Chip Fast Frequency Hopping Synthesizers for Wireless Multi-gigahertz Applications: Design Methodology, Analysis, and Implementation | |
Zarkeshvari et al. | PLL-based fractional-N frequency synthesizers | |
Temporiti et al. | Insights into wideband fractional all-digital PLLs for RF applications | |
Staszewski et al. | Elimination of spurious noise due to time-to-digital converter | |
Albittar et al. | A frequency multiplier for reference frequency in frequency synthesizer systems | |
Pu et al. | A novel fractional-N PLL based on a simple reference multiplier |