Kalb et al., 2016 - Google Patents
Enabling dynamic and partial reconfiguration in Xilinx SDSoCKalb et al., 2016
View PDF- Document ID
- 15668967015160266497
- Author
- Kalb T
- Göhringer D
- Publication year
- Publication venue
- 2016 International Conference on ReConFigurable Computing and FPGAs (ReConFig)
External Links
Snippet
In the past years dynamic partial reconfiguration (DPR) has been established as a well- known technique for systems featuring a field programmable gate array (FPGA). Systems-on- Chip (SoC) with an ARM processor ease the utilization of DPR and motivate its …
- 230000036961 partial 0 title abstract description 34
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING; COUNTING
- G06F—ELECTRICAL DIGITAL DATA PROCESSING
- G06F17/00—Digital computing or data processing equipment or methods, specially adapted for specific functions
- G06F17/50—Computer-aided design
- G06F17/5045—Circuit design
- G06F17/5054—Circuit design for user-programmable logic devices, e.g. field programmable gate arrays [FPGA]
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING; COUNTING
- G06F—ELECTRICAL DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for programme control, e.g. control unit
- G06F9/06—Arrangements for programme control, e.g. control unit using stored programme, i.e. using internal store of processing equipment to receive and retain programme
- G06F9/44—Arrangements for executing specific programmes
- G06F9/455—Emulation; Software simulation, i.e. virtualisation or emulation of application or operating system execution engines
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING; COUNTING
- G06F—ELECTRICAL DIGITAL DATA PROCESSING
- G06F17/00—Digital computing or data processing equipment or methods, specially adapted for specific functions
- G06F17/50—Computer-aided design
- G06F17/5009—Computer-aided design using simulation
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING; COUNTING
- G06F—ELECTRICAL DIGITAL DATA PROCESSING
- G06F8/00—Arrangements for software engineering
- G06F8/40—Transformations of program code
- G06F8/41—Compilation
- G06F8/44—Encoding
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING; COUNTING
- G06F—ELECTRICAL DIGITAL DATA PROCESSING
- G06F8/00—Arrangements for software engineering
- G06F8/30—Creation or generation of source code
- G06F8/34—Graphical or visual programming
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING; COUNTING
- G06F—ELECTRICAL DIGITAL DATA PROCESSING
- G06F8/00—Arrangements for software engineering
- G06F8/30—Creation or generation of source code
- G06F8/36—Software reuse
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING; COUNTING
- G06F—ELECTRICAL DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/36—Preventing errors by testing or debugging software
- G06F11/362—Software debugging
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING; COUNTING
- G06F—ELECTRICAL DIGITAL DATA PROCESSING
- G06F15/00—Digital computers in general; Data processing equipment in general
- G06F15/76—Architectures of general purpose stored programme computers
- G06F15/78—Architectures of general purpose stored programme computers comprising a single central processing unit
- G06F15/7867—Architectures of general purpose stored programme computers comprising a single central processing unit with reconfigurable architecture
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING; COUNTING
- G06F—ELECTRICAL DIGITAL DATA PROCESSING
- G06F8/00—Arrangements for software engineering
- G06F8/70—Software maintenance or management
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING; COUNTING
- G06F—ELECTRICAL DIGITAL DATA PROCESSING
- G06F8/00—Arrangements for software engineering
- G06F8/60—Software deployment
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING; COUNTING
- G06F—ELECTRICAL DIGITAL DATA PROCESSING
- G06F2217/00—Indexing scheme relating to computer aided design [CAD]
- G06F2217/68—Processors
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING; COUNTING
- G06F—ELECTRICAL DIGITAL DATA PROCESSING
- G06F1/00—Details of data-processing equipment not covered by groups G06F3/00 - G06F13/00, e.g. cooling, packaging or power supply specially adapted for computer application
Similar Documents
Publication | Publication Date | Title |
---|---|---|
US7503027B1 (en) | Hardware description language code generation from a state diagram | |
Koch et al. | FPGAs for software programmers | |
Chou et al. | The chinook hardware/software co-synthesis system | |
KR100775547B1 (en) | Automated processor generation system for designing a configurable processor and method for the same | |
EP0853792B1 (en) | Method of producing a digital signal processor | |
US7379861B2 (en) | Dynamic programming of trigger conditions in hardware emulation systems | |
KR20220002644A (en) | Creation of Dynamic Design Flows for Integrated Circuits | |
WO2011156234A1 (en) | Systems and methods for circuit design, synthesis, simulation, and modeling | |
US20130290693A1 (en) | Method and Apparatus for the Automatic Generation of RTL from an Untimed C or C++ Description as a Fine-Grained Specialization of a Micro-processor Soft Core | |
Kalb et al. | Enabling dynamic and partial reconfiguration in Xilinx SDSoC | |
Chattopadhyay et al. | LISA: A uniform ADL for embedded processor modeling, implementation, and software toolsuite generation | |
D'Andrea et al. | Self-adaptive loop for CPSs: is the dynamic partial reconfiguration profitable? | |
Xiao et al. | HiPR: High-level partial reconfiguration for fast incremental FPGA compilation | |
Wang et al. | Automated field-programmable compute accelerator design using partial evaluation | |
Kang et al. | A design and test technique for embedded software | |
Castellana et al. | An automated flow for the high level synthesis of coarse grained parallel applications | |
Wilson et al. | Seiba: An FPGA overlay-based approach to rapid application development | |
Ibellaatti et al. | HERMES: qualification of High pErformance pRogrammable Microprocessor and dEvelopment of Software ecosystem | |
Todman et al. | Verification of streaming hardware and software codesigns | |
Fricke et al. | Automatic tool-flow for mapping applications to an application-specific cgra architecture | |
Zulberti et al. | A script-based cycle-true verification framework to speed-up hardware and software co-design of system-on-chip exploiting RISC-V architecture | |
Lagadec et al. | Model-driven toolset for embedded reconfigurable cores: Flexible prototyping and software-like debugging | |
Groza et al. | A self-reconfigurable platform for built-in self-test applications | |
Guillet et al. | Modeling and formal control of partial dynamic reconfiguration | |
Picard et al. | Multilevel simulation of heterogeneous reconfigurable platforms |