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Lin et al., 2013 - Google Patents

Fabrication of GeSn-on-insulator (GSOI) to enable monolithic 3D co-integration of logic and photonics

Lin et al., 2013

Document ID
15450831567737584156
Author
Lin J
Gupta S
Huang Y
Kim Y
Jin M
Sanchez E
Chen R
Balram K
Miller D
Harris J
Saraswat K
Publication year
Publication venue
2013 Symposium on VLSI Technology

External Links

Snippet

In this work, we demonstrate the low temperature fabrication of high quality GeSn-On- Insulator (GSOI) which forms the crucial module for monolithic 3DIC. The use of GeSn and Ge overcomes many challenges of monolithic 3D integration, including the need for Si …
Continue reading at ieeexplore.ieee.org (other versions)

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    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer, carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
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    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
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