Tanaka et al., 2016 - Google Patents
0.6–1.0 V operation set/reset voltage (3 V) generator for three-dimensional integrated resistive random access memory and NAND flash hybrid solid-state driveTanaka et al., 2016
- Document ID
- 15133389284499397827
- Author
- Tanaka M
- Hachiya S
- Ishii T
- Ning S
- Tsurumi K
- Takeuchi K
- Publication year
- Publication venue
- Japanese Journal of Applied Physics
External Links
Snippet
Abstract A 0.6–1.0 V, 25.9 mm 2 boost converter is proposed to generate resistive random access memory (ReRAM) write (set/reset) voltage for three-dimensional (3D) integrated ReRAM and NAND flash hybrid solid-state drive (SSD). The proposed boost converter uses …
- 238000005265 energy consumption 0 abstract description 31
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING; COUNTING
- G06F—ELECTRICAL DIGITAL DATA PROCESSING
- G06F17/00—Digital computing or data processing equipment or methods, specially adapted for specific functions
- G06F17/50—Computer-aided design
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING; COUNTING
- G06F—ELECTRICAL DIGITAL DATA PROCESSING
- G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
- G06F3/01—Input arrangements or combined input and output arrangements for interaction between user and computer
-
- H—ELECTRICITY
- H01—BASIC ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING; COUNTING
- G06F—ELECTRICAL DIGITAL DATA PROCESSING
- G06F1/00—Details of data-processing equipment not covered by groups G06F3/00 - G06F13/00, e.g. cooling, packaging or power supply specially adapted for computer application
Similar Documents
Publication | Publication Date | Title |
---|---|---|
Linn et al. | Beyond von Neumann—logic operations in passive crossbar arrays alongside memory operations | |
US8476689B2 (en) | Super CMOS devices on a microelectronics system | |
De Sandre et al. | A 4 Mb LV MOS-selected embedded phase change memory in 90 nm standard CMOS technology | |
Shim et al. | Two-step write–verify scheme and impact of the read noise in multilevel RRAM-based inference engine | |
Bavandpour et al. | 3D-aCortex: An ultra-compact energy-efficient neurocomputing platform based on commercial 3D-NAND flash memories | |
Wang et al. | A physics-based compact model of ferroelectric tunnel junction for memory and logic design | |
Kurinec et al. | Nanoscale semiconductor memories: technology and applications | |
Zheng et al. | Memristor-based ternary content addressable memory (mTCAM) for data-intensive computing | |
Egami et al. | Investigation of multi-level-cell and set operations on super-lattice phase change memories | |
Gammaitoni et al. | Towards zero-power ICT | |
Kurokawa et al. | CAAC-IGZO FET/Si-FET hybrid structured analog multiplier and vector-by-matrix multiplier for neural network | |
Ghasemian et al. | HF-QSRAM: half-select free quaternary SRAM design with required peripheral circuits for IoT/IoVT applications | |
Chee et al. | Low energy non-volatile look-up table using 2 bit ReRAM for field programmable gate array | |
Guo et al. | A novel architecture of non-volatile magnetic arithmetic logic unit using magnetic tunnel junctions | |
Soni et al. | Energy efficient ternary computation unit using differential spin Hall effect MRAM | |
Tanaka et al. | 0.6–1.0 V operation set/reset voltage (3 V) generator for three-dimensional integrated resistive random access memory and NAND flash hybrid solid-state drive | |
Suzuki et al. | Design of a magnetic-tunnel-junction-oriented nonvolatile lookup table circuit with write-operation-minimized data shifting | |
Xu et al. | Ferroelectric FET-based context-switching FPGA enabling dynamic reconfiguration for adaptive deep learning machines | |
Natsui et al. | Impact of MTJ-based nonvolatile circuit techniques for energy-efficient binary neural network hardware | |
Han et al. | A novel ternary content addressable memory design based on resistive random access memory with high intensity and low search energy | |
Li et al. | Impact of variations of threshold voltage and hold voltage of threshold switching selectors in 1S1R crossbar array | |
Suzuki et al. | Design of a highly reliable, high-speed MTJ-based lookup table circuit using fractured logic-in-memory structure | |
ul Haq et al. | Energy-efficient design of quaternary logic gates and arithmetic circuits using hybrid CNTFET-RRAM technology | |
Bai et al. | Architecture optimization of nanobridge-based field-programmable gate array and its evaluation | |
Ohsawa et al. | A two-transistor bootstrap type selective device for spin-transfer-torque magnetic tunnel junctions |