[go: up one dir, main page]
More Web Proxy on the site http://driver.im/

Rai et al., 2011 - Google Patents

A New Power Gating Structure for Low Voltage Low Power MTCMOS Design

Rai et al., 2011

Document ID
15089285041174235832
Author
Rai S
Shrivastava P
Patro M
Mishra R
Tiwari S
Publication year

External Links

Snippet

Scaling and power reduction trends in present technology causes sub threshold leakage currents to become an increasingly large component of total power dissipation. This paper presents Multi-threshold voltage technique for reducing standby power dissipation while still …
Continue reading at asmedigitalcollection.asme.org (other versions)

Classifications

    • GPHYSICS
    • G06COMPUTING; CALCULATING; COUNTING
    • G06FELECTRICAL DIGITAL DATA PROCESSING
    • G06F1/00Details of data-processing equipment not covered by groups G06F3/00 - G06F13/00, e.g. cooling, packaging or power supply specially adapted for computer application
    • G06F1/26Power supply means, e.g. regulation thereof
    • G06F1/32Means for saving power
    • G06F1/3203Power Management, i.e. event-based initiation of power-saving mode
    • G06F1/3234Action, measure or step performed to reduce power consumption
    • G06F1/3287Power saving by switching off individual functional units in a computer system, i.e. selective power distribution
    • HELECTRICITY
    • H03BASIC ELECTRONIC CIRCUITRY
    • H03KPULSE TECHNIQUE
    • H03K19/00Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/0008Arrangements for reducing power consumption
    • H03K19/0016Arrangements for reducing power consumption by using a control or a clock signal, e.g. in order to apply power supply
    • GPHYSICS
    • G06COMPUTING; CALCULATING; COUNTING
    • G06FELECTRICAL DIGITAL DATA PROCESSING
    • G06F17/00Digital computing or data processing equipment or methods, specially adapted for specific functions
    • G06F17/50Computer-aided design
    • G06F17/5009Computer-aided design using simulation
    • GPHYSICS
    • G06COMPUTING; CALCULATING; COUNTING
    • G06FELECTRICAL DIGITAL DATA PROCESSING
    • G06F1/00Details of data-processing equipment not covered by groups G06F3/00 - G06F13/00, e.g. cooling, packaging or power supply specially adapted for computer application
    • G06F1/16Constructional details or arrangements
    • HELECTRICITY
    • H03BASIC ELECTRONIC CIRCUITRY
    • H03KPULSE TECHNIQUE
    • H03K3/00Circuits for generating electric pulses; Monostable, bistable or multistable circuits
    • H03K3/02Generators characterised by the type of circuit or by the means used for producing pulses
    • GPHYSICS
    • G06COMPUTING; CALCULATING; COUNTING
    • G06FELECTRICAL DIGITAL DATA PROCESSING
    • G06F7/00Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F7/38Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
    • GPHYSICS
    • G06COMPUTING; CALCULATING; COUNTING
    • G06FELECTRICAL DIGITAL DATA PROCESSING
    • G06F2217/00Indexing scheme relating to computer aided design [CAD]
    • G06F2217/78Power analysis and optimization
    • HELECTRICITY
    • H03BASIC ELECTRONIC CIRCUITRY
    • H03KPULSE TECHNIQUE
    • H03K19/00Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/003Modifications for increasing the reliability for protection
    • HELECTRICITY
    • H03BASIC ELECTRONIC CIRCUITRY
    • H03KPULSE TECHNIQUE
    • H03K17/00Electronic switching or gating, i.e. not by contact-making or -braking

Similar Documents

Publication Publication Date Title
Kao et al. Dual-threshold voltage techniques for low-power digital circuits
Tschanz et al. Dynamic sleep transistor and body bias for active leakage power control of microprocessors
Sharma A survey of leakage reduction techniques in CMOS digital circuits for nanoscale regime
Dhar et al. Design of an energy efficient, high speed, low power full subtractor using GDI technique
Kosonocky et al. Low-power circuits and technology for wireless digital systems
Jalan et al. Analysis of leakage power reduction techniques in digital circuits
Liu et al. PMOS-only sleep switch dual-threshold voltage domino logic in sub-65-nm CMOS technologies
Kumar et al. Performance of a two input nand gate using subthreshold leakage control techniques
Min et al. Leakage-suppressed clock-gating circuit with zigzag super cut-off cmos (zsccmos) for leakage-dominant sub-70-nm and sub-1-vv/sub dd/lsis
Dadoria et al. A novel approach for leakage power reduction in deep submicron technologies in CMOS VLSI circuits
Moghaddam et al. A low-power multiplier using an efficient single-supply voltage level converter
Rai et al. A New Power Gating Structure for Low Voltage Low Power MTCMOS Design
Murthy et al. A novel design of multiplexer based full-adder cell for power and propagation delay optimizations
Kim et al. Low-power carry look-ahead adder with multi-threshold voltage CMOS technology
Raj et al. An effective design technique to reduce leakage power
Pattanaik et al. Ground bounce noise reduction of low leakage 1-bit nano-CMOS based full adder cells for mobile applications
Kumar Dynamic power dissipation analysis in CMOS VLSI circuit design with scaling down in technology
Sreenivasulu et al. Ground bouncing noise reduction in combinational MTCMOS circuits
Saha et al. A low-voltage, Low-Power 4-bit BCD adder, designed using the Clock Gated Power Gating, and the DVT scheme
Hussain et al. An energy efficient and fast hybrid full adder circuit
Thuraka High Performance Arithmetic and Logic Unit with Enhanced MTCMOS and Transistor Stacking Techniques
Goyal Characterizing processors for time and energy optimization
Gunthakalla Methodologies for high-speed and low-power VLSI design
Eratne et al. Leakage control in full adders with selectively stacked inverters
Verma et al. Power Optimization in CMOS based EX-OR Gate using Pass Transistor Technique