[go: up one dir, main page]
More Web Proxy on the site http://driver.im/

Hoseini et al., 2014 - Google Patents

Macro modeling approach for semi-digital smart integrated circuits

Hoseini et al., 2014

Document ID
14930885036451121240
Author
Hoseini Z
Lee K
Kim B
Publication year
Publication venue
Frontier and innovation in future computing and communications

External Links

Snippet

This work presents a macro modeling approach for semi-digital smart integrated circuits. The proposed macro model models the behavior of the key circuit block used for semi-digital smart integrated circuits which is the time-to-voltage converter. Furthermore, the macro …
Continue reading at link.springer.com (other versions)

Classifications

    • GPHYSICS
    • G06COMPUTING; CALCULATING; COUNTING
    • G06FELECTRICAL DIGITAL DATA PROCESSING
    • G06F17/00Digital computing or data processing equipment or methods, specially adapted for specific functions
    • G06F17/50Computer-aided design
    • G06F17/5009Computer-aided design using simulation
    • G06F17/5036Computer-aided design using simulation for analog modelling, e.g. for circuits, spice programme, direct methods, relaxation methods
    • GPHYSICS
    • G06COMPUTING; CALCULATING; COUNTING
    • G06FELECTRICAL DIGITAL DATA PROCESSING
    • G06F17/00Digital computing or data processing equipment or methods, specially adapted for specific functions
    • G06F17/30Information retrieval; Database structures therefor; File system structures therefor
    • G06F17/30861Retrieval from the Internet, e.g. browsers
    • GPHYSICS
    • G06COMPUTING; CALCULATING; COUNTING
    • G06FELECTRICAL DIGITAL DATA PROCESSING
    • G06F7/00Methods or arrangements for processing data by operating upon the order or content of the data handled

Similar Documents

Publication Publication Date Title
Sabarathinam et al. Implementation and study of the nonlinear dynamics of a memristor-based Duffing oscillator
Vista et al. High frequency meminductor emulator employing VDTA and its application
Minaei et al. Memstor, memstance simulations via a versatile 4-port built with new adder and subtractor circuits
US20140282314A1 (en) Intelligent metamodel integrated verilog-ams for fast and accurate analog block design exploration
Pandey et al. Current mode full‐wave rectifier based on a single MZC‐CDTA
Konal et al. Electronically controllable memcapacitor emulator employing VDCCs
Barra et al. Simulink behavioral modeling of a 10-bit pipelined ADC
Vural et al. Process independent automated sizing methodology for current steering DAC
Hoseini et al. Macro modeling approach for semi-digital smart integrated circuits
Vlassis et al. Automatic tuning circuit for bulk‐controlled subthreshold MOS resistors
Benko et al. Innovative approach for electrical characterisation of pseudo‐resistors
Yongda et al. Threshold‐voltage‐difference‐based CMOS voltage reference derived from basic current bias generator with 4.3 ppm/° C temperature coefficient
Purushothaman et al. A new delay model and geometric programming-based design automation for latched comparators
Zardalidis et al. Design and simulation of a nanoelectronic single electron 2–4 decoder using a novel simulator
Agarwal et al. Design and simulation of octal-to-binary encoder using capacitive single-electron transistors (C-SETs)
Arnaud et al. Bulk linearisation of the MOS resistor
Soni et al. Highly accurate memristor modelling using MOS transistor for analog applications
Ray et al. Switching architecture for CMOS exponential function generators eliminating squarer/multiplier circuits
Kazmierski et al. A fast, numerical circuit-level model of carbon nanotube transistor
D'Angelo et al. Analogue multiplier using passive circuits and digital primitives with time‐mode signal representation
Duan et al. On chip signal generators for low overhead ADC BIST
Rodrigues et al. Hysteresis settling technique for CMOS comparators based on substrate voltage
Abe et al. Highly-integrable analogue reservoir circuits based on a simple cycle architecture
Leitner et al. Digital LDO modelling techniques for performance estimation at early design stage
French Modeling and Simulation of Hybrid Single Electron and Field Effect Transistor Circuits for Future Low Power Nanoelectronics