[go: up one dir, main page]
More Web Proxy on the site http://driver.im/

Rath et al., 1994 - Google Patents

Specification and synthesis of bounded indirection,"

Rath et al., 1994

View PDF
Document ID
14963048664911609189
Author
Rath K
Tuna M
Johnson S
Publication year

External Links

Snippet

In this paper, we introduce bounded indirection, a restricted form of pointers, for system speci cation. Indirection provides a mechanism for compact descriptions of many complex control structures, such as interrupts, continuations, and dynamic connections between …
Continue reading at cs.indiana.edu (PDF) (other versions)

Classifications

    • GPHYSICS
    • G06COMPUTING; CALCULATING; COUNTING
    • G06FELECTRICAL DIGITAL DATA PROCESSING
    • G06F17/00Digital computing or data processing equipment or methods, specially adapted for specific functions
    • G06F17/50Computer-aided design
    • G06F17/5045Circuit design
    • G06F17/505Logic synthesis, e.g. technology mapping, optimisation
    • GPHYSICS
    • G06COMPUTING; CALCULATING; COUNTING
    • G06FELECTRICAL DIGITAL DATA PROCESSING
    • G06F17/00Digital computing or data processing equipment or methods, specially adapted for specific functions
    • G06F17/50Computer-aided design
    • G06F17/5009Computer-aided design using simulation
    • G06F17/5022Logic simulation, e.g. for logic circuit operation
    • GPHYSICS
    • G06COMPUTING; CALCULATING; COUNTING
    • G06FELECTRICAL DIGITAL DATA PROCESSING
    • G06F17/00Digital computing or data processing equipment or methods, specially adapted for specific functions
    • G06F17/50Computer-aided design
    • G06F17/5045Circuit design
    • G06F17/5054Circuit design for user-programmable logic devices, e.g. field programmable gate arrays [FPGA]
    • GPHYSICS
    • G06COMPUTING; CALCULATING; COUNTING
    • G06FELECTRICAL DIGITAL DATA PROCESSING
    • G06F17/00Digital computing or data processing equipment or methods, specially adapted for specific functions
    • G06F17/50Computer-aided design
    • G06F17/5068Physical circuit design, e.g. layout for integrated circuits or printed circuit boards
    • GPHYSICS
    • G06COMPUTING; CALCULATING; COUNTING
    • G06FELECTRICAL DIGITAL DATA PROCESSING
    • G06F17/00Digital computing or data processing equipment or methods, specially adapted for specific functions
    • G06F17/30Information retrieval; Database structures therefor; File system structures therefor
    • GPHYSICS
    • G06COMPUTING; CALCULATING; COUNTING
    • G06FELECTRICAL DIGITAL DATA PROCESSING
    • G06F9/00Arrangements for programme control, e.g. control unit
    • G06F9/06Arrangements for programme control, e.g. control unit using stored programme, i.e. using internal store of processing equipment to receive and retain programme
    • GPHYSICS
    • G06COMPUTING; CALCULATING; COUNTING
    • G06FELECTRICAL DIGITAL DATA PROCESSING
    • G06F2217/00Indexing scheme relating to computer aided design [CAD]
    • G06F2217/78Power analysis and optimization
    • GPHYSICS
    • G06COMPUTING; CALCULATING; COUNTING
    • G06FELECTRICAL DIGITAL DATA PROCESSING
    • G06F15/00Digital computers in general; Data processing equipment in general
    • G06F15/76Architectures of general purpose stored programme computers
    • GPHYSICS
    • G06COMPUTING; CALCULATING; COUNTING
    • G06FELECTRICAL DIGITAL DATA PROCESSING
    • G06F3/00Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • GPHYSICS
    • G06COMPUTING; CALCULATING; COUNTING
    • G06FELECTRICAL DIGITAL DATA PROCESSING
    • G06F1/00Details of data-processing equipment not covered by groups G06F3/00 - G06F13/00, e.g. cooling, packaging or power supply specially adapted for computer application
    • GPHYSICS
    • G06COMPUTING; CALCULATING; COUNTING
    • G06FELECTRICAL DIGITAL DATA PROCESSING
    • G06F7/00Methods or arrangements for processing data by operating upon the order or content of the data handled
    • GPHYSICS
    • G06COMPUTING; CALCULATING; COUNTING
    • G06FELECTRICAL DIGITAL DATA PROCESSING
    • G06F11/00Error detection; Error correction; Monitoring

Similar Documents

Publication Publication Date Title
EP0701713B1 (en) Field programmable logic device with dynamic interconnections to a dynamic logic core
US7530047B2 (en) Optimized mapping of an integrated circuit design to multiple cell libraries during a single synthesis pass
Arnold The Splash 2 software environment
US5903466A (en) Constraint driven insertion of scan logic for implementing design for test within an integrated circuit design
US7987086B2 (en) Software entity for the creation of a hybrid cycle simulation model
Gschwind et al. FPGA prototyping of a RISC processor core for embedded applications
US7143376B1 (en) Method and apparatus for design verification with equivalency check
JP2003518666A (en) A method for implementing physical design for dynamically reconfigurable logic circuits.
JP2006286000A (en) Manufacturing method for equivalent filed programmable gate array and integrated circuit for structured specification purpose
WO2007071506A1 (en) A method for multi-cycle clock gating
US8248869B1 (en) Configurable memory map interface and method of implementing a configurable memory map interface
JP2000057201A (en) Method and system for sharing limited register for low power vlsi design
Reese et al. Introduction to logic synthesis using Verilog HDL
US6834379B2 (en) Timing path detailer
Rath et al. Specification and synthesis of bounded indirection,"
Poole Self-timed logic circuits
Farnsworth et al. A hybrid asynchronous system design environment
US7194708B2 (en) Generation of clock gating function for synchronous circuit
Tuna et al. Specification and synthesis of bounded indirection
US20070006105A1 (en) Method and system for synthesis of flip-flops
US7131090B2 (en) Clocked gating based on measured performance
US7945433B2 (en) Hardware simulation accelerator design and method that exploits a parallel structure of user models to support a larger user model size
US20040153977A1 (en) Clock gating for hierarchical structure
US20040230923A1 (en) Generation of improved input function for clocked element in synchronous circuit
Greiner et al. Design of a high complexity superscalar microprocessor with the portable IDPS ASIC library