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Dumitrescu et al., 1998 - Google Patents

Identification of non-redundant memorizing elements in VHDL synchronous designs for formal verification tools

Dumitrescu et al., 1998

View PDF
Document ID
1481145012120967941
Author
Dumitrescu E
Ostier P
Publication year
Publication venue
Proceedings of the Fifth International Workshop on Symbolic Methods and Applications in Circuit Design (SMACD)

External Links

Snippet

Formal tools for the verification of HDL synchronous descriptions are currently in development for both the Verilog [2, 3] and VHDL languages [1], but little work has been done on tools able to handle both languages [8]. The well known reason is that VHDL and …
Continue reading at citeseerx.ist.psu.edu (PDF) (other versions)

Classifications

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    • G06F17/50—Computer-aided design
    • G06F17/5009—Computer-aided design using simulation
    • G06F17/504—Formal methods
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING; COUNTING
    • G06F—ELECTRICAL DIGITAL DATA PROCESSING
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    • G06F17/50—Computer-aided design
    • G06F17/5009—Computer-aided design using simulation
    • G06F17/5022—Logic simulation, e.g. for logic circuit operation
    • G06F17/5031—Timing analysis
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    • G06F17/5054—Circuit design for user-programmable logic devices, e.g. field programmable gate arrays [FPGA]
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