Nii et al., 2011 - Google Patents
Future TechnologiesNii et al., 2011
- Document ID
- 14441764545303645480
- Author
- Nii K
- Yamaoka M
- Publication year
- Publication venue
- Low Power and Reliable SRAM Memory Cell and Array Design
External Links
Snippet
The design solution described in Chap. 5 will help the minimum operating voltage (VDD min) of a general 6T single-port SRAM. However, it will eventually face the limitation of the SRAM VDD min because of the degradation of the SRAM stability due to an increase in the …
- 230000015556 catabolic process 0 abstract description 3
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- G11C11/417—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing, timing, power reduction for memory cells of the field-effect type
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- G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
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