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Canis et al., 2014 - Google Patents

Modulo SDC scheduling with recurrence minimization in high-level synthesis

Canis et al., 2014

View PDF
Document ID
1434588598452082383
Author
Canis A
Brown S
Anderson J
Publication year
Publication venue
2014 24th International Conference on Field Programmable Logic and Applications (FPL)

External Links

Snippet

Loop pipelining is a high-level synthesis scheduling technique that overlaps loop iterations to achieve higher performance. However, industrial designs often have resource constraints and other constraints imposed by cross-iteration dependencies. The interaction between …
Continue reading at janders.eecg.toronto.edu (PDF) (other versions)

Classifications

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    • G06F9/46—Multiprogramming arrangements
    • G06F9/48—Programme initiating; Programme switching, e.g. by interrupt
    • G06F9/4806—Task transfer initiation or dispatching
    • G06F9/4843—Task transfer initiation or dispatching by program, e.g. task dispatcher, supervisor, operating system
    • G06F9/4881—Scheduling strategies for dispatcher, e.g. round robin, multi-level priority queues
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    • G06F9/5038—Allocation of resources, e.g. of the central processing unit [CPU] to service a request the resource being a machine, e.g. CPUs, Servers, Terminals considering the execution order of a plurality of tasks, e.g. taking priority or time dependency constraints into consideration
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