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Myers et al., 1993 - Google Patents

Synthesis of timed asynchronous circuits

Myers et al., 1993

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Document ID
14267020595618143201
Author
Myers C
Meng T
Publication year
Publication venue
IEEE Transactions on Very Large Scale Integration (VLSI) Systems

External Links

Snippet

The authors present a systematic procedure for synthesizing timed asynchronous circuits using timing constraints dictated by system integration, thereby facilitating natural interaction between synchronous and asynchronous circuits. Their timed circuits also tend to be more …
Continue reading at core.ac.uk (PDF) (other versions)

Classifications

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    • G06F17/5022—Logic simulation, e.g. for logic circuit operation
    • G—PHYSICS
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