Wang et al., 2019 - Google Patents
A scalable spatial skyline evaluation system utilizing parallel independent region groupsWang et al., 2019
View PDF- Document ID
- 13901930964102994952
- Author
- Wang W
- Zhang J
- Sun M
- Ku W
- Publication year
- Publication venue
- The VLDB Journal
External Links
Snippet
This research presents two parallel solutions to efficiently address spatial skyline queries. First, we propose a novel concept called independent regions for parallelizing the process of spatial skyline evaluation. Spatial skyline candidates in an independent region do not …
- 238000011156 evaluation 0 title abstract description 28
Classifications
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- G06F17/30312—Storage and indexing structures; Management thereof
- G06F17/30321—Indexing structures
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- G—PHYSICS
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- G06F9/00—Arrangements for programme control, e.g. control unit
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- G06F9/46—Multiprogramming arrangements
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- G06F17/30386—Retrieval requests
- G06F17/30424—Query processing
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- G06—COMPUTING; CALCULATING; COUNTING
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- G06F17/30—Information retrieval; Database structures therefor; File system structures therefor
- G06F17/30943—Information retrieval; Database structures therefor; File system structures therefor details of database functions independent of the retrieved data type
- G06F17/30946—Information retrieval; Database structures therefor; File system structures therefor details of database functions independent of the retrieved data type indexing structures
- G06F17/30961—Trees
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- G—PHYSICS
- G06—COMPUTING; CALCULATING; COUNTING
- G06F—ELECTRICAL DIGITAL DATA PROCESSING
- G06F12/00—Accessing, addressing or allocating within memory systems or architectures
- G06F12/02—Addressing or allocation; Relocation
- G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
- G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
- G06F12/0806—Multiuser, multiprocessor or multiprocessing cache systems
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- G—PHYSICS
- G06—COMPUTING; CALCULATING; COUNTING
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- G06F15/00—Digital computers in general; Data processing equipment in general
- G06F15/16—Combinations of two or more digital computers each having at least an arithmetic unit, a programme unit and a register, e.g. for a simultaneous processing of several programmes
- G06F15/163—Interprocessor communication
- G06F15/173—Interprocessor communication using an interconnection network, e.g. matrix, shuffle, pyramid, star, snowflake
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- G06F15/76—Architectures of general purpose stored programme computers
- G06F15/80—Architectures of general purpose stored programme computers comprising an array of processing units with common control, e.g. single instruction multiple data processors
- G06F15/8007—Architectures of general purpose stored programme computers comprising an array of processing units with common control, e.g. single instruction multiple data processors single instruction multiple data [SIMD] multiprocessors
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