Li et al., 2020 - Google Patents
DC IR-drop analysis of multilayered power distribution network by discontinuous Galerkin method with thermal effects incorporatedLi et al., 2020
View PDF- Document ID
- 13991575171746256635
- Author
- Li P
- Tang M
- Huang Z
- Jiang L
- Bağcı H
- Publication year
- Publication venue
- IEEE Transactions on Components, Packaging and Manufacturing Technology
External Links
Snippet
Due to the temperature-dependent resistivity of power distribution network (PDN) interconnects, a wiser and necessary strategy is to proceed the electrical–thermal cosimulation in order to include the thermal effects caused by Joule heating. As a natural …
- 230000000694 effects 0 title abstract description 26
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING; COUNTING
- G06F—ELECTRICAL DIGITAL DATA PROCESSING
- G06F17/00—Digital computing or data processing equipment or methods, specially adapted for specific functions
- G06F17/50—Computer-aided design
- G06F17/5009—Computer-aided design using simulation
- G06F17/5036—Computer-aided design using simulation for analog modelling, e.g. for circuits, spice programme, direct methods, relaxation methods
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING; COUNTING
- G06F—ELECTRICAL DIGITAL DATA PROCESSING
- G06F17/00—Digital computing or data processing equipment or methods, specially adapted for specific functions
- G06F17/50—Computer-aided design
- G06F17/5009—Computer-aided design using simulation
- G06F17/5018—Computer-aided design using simulation using finite difference methods or finite element methods
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING; COUNTING
- G06F—ELECTRICAL DIGITAL DATA PROCESSING
- G06F17/00—Digital computing or data processing equipment or methods, specially adapted for specific functions
- G06F17/50—Computer-aided design
- G06F17/5068—Physical circuit design, e.g. layout for integrated circuits or printed circuit boards
- G06F17/5081—Layout analysis, e.g. layout verification, design rule check
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING; COUNTING
- G06F—ELECTRICAL DIGITAL DATA PROCESSING
- G06F17/00—Digital computing or data processing equipment or methods, specially adapted for specific functions
- G06F17/50—Computer-aided design
- G06F17/5045—Circuit design
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING; COUNTING
- G06F—ELECTRICAL DIGITAL DATA PROCESSING
- G06F2217/00—Indexing scheme relating to computer aided design [CAD]
- G06F2217/16—Numerical modeling
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING; COUNTING
- G06F—ELECTRICAL DIGITAL DATA PROCESSING
- G06F2217/00—Indexing scheme relating to computer aided design [CAD]
- G06F2217/78—Power analysis and optimization
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING; COUNTING
- G06F—ELECTRICAL DIGITAL DATA PROCESSING
- G06F2217/00—Indexing scheme relating to computer aided design [CAD]
- G06F2217/04—CAD in a network environment
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING; COUNTING
- G06F—ELECTRICAL DIGITAL DATA PROCESSING
- G06F2217/00—Indexing scheme relating to computer aided design [CAD]
- G06F2217/80—Thermal analysis and optimization
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING; COUNTING
- G06F—ELECTRICAL DIGITAL DATA PROCESSING
- G06F2217/00—Indexing scheme relating to computer aided design [CAD]
- G06F2217/02—Component-based CAD
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING; COUNTING
- G06F—ELECTRICAL DIGITAL DATA PROCESSING
- G06F2217/00—Indexing scheme relating to computer aided design [CAD]
- G06F2217/82—Noise analysis and optimization
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING; COUNTING
- G06F—ELECTRICAL DIGITAL DATA PROCESSING
- G06F2217/00—Indexing scheme relating to computer aided design [CAD]
- G06F2217/40—Chip packaging
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING; COUNTING
- G06F—ELECTRICAL DIGITAL DATA PROCESSING
- G06F2217/00—Indexing scheme relating to computer aided design [CAD]
- G06F2217/12—Design for manufacturability
Similar Documents
Publication | Publication Date | Title |
---|---|---|
Li et al. | DC IR-drop analysis of multilayered power distribution network by discontinuous Galerkin method with thermal effects incorporated | |
Xie et al. | Electrical–thermal cosimulation with nonconformal domain decomposition method for multiscale 3-D integrated systems | |
Liu et al. | Compact lateral thermal resistance model of TSVs for fast finite-difference based thermal analysis of 3-D stacked ICs | |
Li et al. | Transient analysis of dispersive power-ground plate pairs with arbitrarily shaped antipads by the DGTD method with wave port excitation | |
Li et al. | Transient thermal analysis of 3-D integrated circuits packages by the DGTD method | |
Zhang et al. | A modeling methodology for thermal analysis of the PCB structure | |
Qian et al. | Fast Poisson solvers for thermal analysis | |
Zhang et al. | Electromagnetic-circuital-thermal multiphysics simulation method: A review | |
Wang et al. | Variability analysis of crosstalk among differential vias using polynomial-chaos and response surface methods | |
Bandinelli et al. | A surface PEEC formulation for high-fidelity analysis of the current return networks in composite aircrafts | |
Li et al. | An efficient mode-based domain decomposition hybrid 2-D/Q-2D finite-element time-domain method for power/ground plate-pair analysis | |
Fan et al. | Modeling DC power-bus structures with vertical discontinuities using a circuit extraction approach based on a mixed-potential integral equation | |
Lombardi et al. | Electrothermal formulation of the partial element equivalent circuit method | |
Yang et al. | DC IR-drop analysis of power distribution networks by a Robin transmission condition-enhanced discontinuous Galerkin method | |
Xie et al. | Electrical–thermal modeling of through‐silicon via (TSV) arrays in interposer | |
Romano et al. | Efficient PEEC iterative solver for power electronic applications | |
Antonini et al. | The Partial Elements Equivalent Circuit Method: The State of the Art | |
Shao et al. | Thermal-aware DC IR-drop co-analysis using non-conformal domain decomposition methods | |
Xie et al. | System-level thermal modeling using nonconformal domain decomposition and model-order reduction | |
Zhu et al. | An SIE formulation with triangular discretization and loop analysis for parameter extraction of arbitrarily shaped interconnects | |
Xie et al. | 3D transient thermal solver using non-conformal domain decomposition approach | |
Xie et al. | FDFD modeling of signal paths with TSVs in silicon interposer | |
Zeng et al. | Matrix-free method for transient maxwell-thermal cosimulation in arbitrary unstructured meshes | |
Min et al. | Electrical-thermal co-analysis of through silicon via with equivalent circuit model | |
Min et al. | Lumped 3-D equivalent thermal circuit model for transient thermal analysis of TSV array |