Kavitha et al., 2019 - Google Patents
16-Layer PCB Channel Design with Minimum Crosstalk and Optimization of VIA and TDR AnalysisKavitha et al., 2019
- Document ID
- 13530118799872534180
- Author
- Kavitha A
- Kaitepalli C
- Swaminathan J
- Ahemedali S
- Publication year
- Publication venue
- Journal of Electronic Testing
External Links
Snippet
A transparent interconnects on a 16 layer PCB stack-up with a 100 Ω differential impedance with interconnects is proposed in this paper. To minimize the differential crosstalk, a differential spacing is maintained between interconnects. The transmitter and receiver are …
- 238000004458 analytical method 0 title abstract description 21
Classifications
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/0213—Electrical arrangements not otherwise provided for
- H05K1/0237—High frequency adaptations
- H05K1/0245—Lay-out of balanced signal pairs, e.g. differential lines or twisted lines
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/0213—Electrical arrangements not otherwise provided for
- H05K1/0237—High frequency adaptations
- H05K1/025—Impedance arrangements, e.g. impedance matching, reduction of parasitic impedance
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/0213—Electrical arrangements not otherwise provided for
- H05K1/0216—Reduction of cross-talk, and noise or electromagnetic interference
- H05K1/0218—Reduction of cross-talk, and noise or electromagnetic interference by printed shielding conductors, ground planes or power plane
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/09—Shape and layout
- H05K2201/09209—Shape and layout details of conductors
- H05K2201/09654—Shape and layout details of conductors covering at least two types of conductors provided for in H05K2201/09218 - H05K2201/095
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/09—Shape and layout
- H05K2201/09209—Shape and layout details of conductors
- H05K2201/095—Conductive through-holes or vias
- H05K2201/09618—Via fence, i.e. one-dimensional array of vias
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/09—Shape and layout
- H05K2201/09209—Shape and layout details of conductors
- H05K2201/0929—Conductive planes
- H05K2201/09309—Core having two or more power planes; Capacitive laminate of two power planes
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/09—Shape and layout
- H05K2201/09209—Shape and layout details of conductors
- H05K2201/095—Conductive through-holes or vias
- H05K2201/09627—Special connections between adjacent vias, not for grounding vias
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/09—Shape and layout
- H05K2201/09209—Shape and layout details of conductors
- H05K2201/09218—Conductive traces
- H05K2201/09236—Parallel layout
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/11—Printed elements for providing electric connections to or between printed circuits
- H05K1/115—Via connections; Lands around holes or via connections
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/0296—Conductive pattern lay-out details not covered by sub groups H05K1/02 - H05K1/0295
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/07—Electric details
- H05K2201/0707—Shielding
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/40—Forming printed elements for providing electric connections to or between printed circuits
- H05K3/42—Plated through-holes or plated via connections
- H05K3/429—Plated through-holes specially for multilayer circuits, e.g. having connections to inner circuit layers
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K9/00—Screening of apparatus or components against electric or magnetic fields
- H05K9/0007—Casings
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING; COUNTING
- G06F—ELECTRICAL DIGITAL DATA PROCESSING
- G06F17/00—Digital computing or data processing equipment or methods, specially adapted for specific functions
- G06F17/50—Computer-aided design
Similar Documents
Publication | Publication Date | Title |
---|---|---|
JP4371065B2 (en) | Transmission line, communication apparatus, and wiring formation method | |
JP6133884B2 (en) | Printed circuit board with embedded electrical passive element for high frequency transmission | |
WO2007102597A1 (en) | Broadband transition from a via interconnection to a planar transmission line in a multilayer substrate | |
WO2014115578A1 (en) | Printed wiring board, electronic device, and wiring connection method | |
Lin et al. | Using stepped-impedance lines for common-mode noise reduction on bended coupled transmission lines | |
Yee et al. | Techniques of impedance matching for minimal PCB channel loss at 40 GBPS signal transmission | |
Engin et al. | Power transmission lines: A new interconnect design to eliminate simultaneous switching noise | |
Packianathan et al. | Performance analysis of microstriplines interconnect structure with novel guard trace as parallel links for high speed dram interfaces | |
Lim et al. | ASIC package design optimization for 10 Gbps and above backplane SerDes links | |
CN107396541B (en) | A method of optimization video signal cable impedance matching | |
Carmona-Cruz et al. | Via transition optimization using a domain decomposition approach | |
US7307492B2 (en) | Design, layout and method of manufacture for a circuit that taps a differential signal | |
Kavitha et al. | 16-Layer PCB Channel Design with Minimum Crosstalk and Optimization of VIA and TDR Analysis | |
Xiangyang et al. | Transmission characteristics of via holes in high-speed PCB | |
Shiue et al. | Significant reduction of common-mode noise in weakly coupled differential serpentine delay microstrip lines using different-layer-routing-turned traces | |
Rowlands et al. | Simulation and measurement of high speed serial link performance in a dense, thin core flip chip package | |
Ryu et al. | Signal Integrity Analysis of Notch-Routing to Reduce Near-End Crosstalk for Tightly Coupled and Short Microstrip Channel | |
Myers et al. | Signal Integrity Considerations of PCB Wiring in Tightly Pitched Module Pin Fields of High Speed Channels | |
Steenbergen et al. | 3D Full-Wave Simulation of Stub Length Effect of Vias in High Speed PCB Design | |
Fukumori et al. | Characterization of signal via structure in multilayer printed circuit boards up to 50 GHz | |
Bai et al. | Analysis of Power-via-Induced Quasi-Quarter-Wavelength Resonance to Reduce Crosstalk | |
Kaveri et al. | Signal Integrity Evaluation for Automotive ECU with PCIe Gen 3.0 Interface | |
US8669830B2 (en) | Method and device for routing over a void for high speed signal routing in electronic systems | |
Kim et al. | Ultra-Wideband Vertical Transition in Coplanar Stripline for Ultra-High-Speed Digital Interfaces | |
Le et al. | Built-in Ring Transmission Line Structure for Signal Integrity Optimization of PAM4 Signaling in PCBs |