Mehlhorn et al., 1983 - Google Patents
Area—Time optimal VLSI integer multiplier with minimum computation timeMehlhorn et al., 1983
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- 13595647301711426018
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- Mehlhorn K
- Preparata F
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According to VLSI theory,[log n,√ n] is the range of computation times for which there may exist an AT 2-optimal multiplier of n-bit integers. Such networks were previously known for the time range [Ω (log 2 n), O (√ n)]; this theoretical question is settled, by exhibition of a …
- 125000004122 cyclic group 0 description 13
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- G06F—ELECTRICAL DIGITAL DATA PROCESSING
- G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
- G06F7/38—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
- G06F7/48—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
- G06F7/52—Multiplying; Dividing
- G06F7/523—Multiplying only
- G06F7/53—Multiplying only in parallel-parallel fashion, i.e. both operands being entered in parallel
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- G06F17/14—Fourier, Walsh or analogous domain transformations, e.g. Laplace, Hilbert, Karhunen-Loeve, transforms
- G06F17/141—Discrete Fourier transforms
- G06F17/142—Fast Fourier transforms, e.g. using a Cooley-Tukey type algorithm
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- G06F7/52—Multiplying; Dividing
- G06F7/523—Multiplying only
- G06F7/533—Reduction of the number of iteration steps or stages, e.g. using the Booth algorithm, log-sum, odd-even
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