Pan et al., 2003 - Google Patents
Flip chip electrical interconnection by selective electroplating and bondingPan et al., 2003
View PDF- Document ID
- 13499263217095354538
- Author
- Pan L
- Yuen P
- Lin L
- Garcia E
- Publication year
- Publication venue
- Microsystem Technologies
External Links
Snippet
This work presents a parallel electrical interconnection process by means of flip-chip, selective electroplating and bonding. The electrical interconnection lines are built on a glass substrate made of 500/2000 Å of Cr/Au with 3150 μm in length and 10 μm in width. Two …
- 238000009713 electroplating 0 title abstract description 17
Classifications
-
- H—ELECTRICITY
- H01—BASIC ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
- H01L2224/13001—Core members of the bump connector
- H01L2224/13005—Structure
- H01L2224/13009—Bump connector integrally formed with a via connection of the semiconductor or solid-state body
-
- H—ELECTRICITY
- H01—BASIC ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/10—Bump connectors ; Manufacturing methods related thereto
- H01L24/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
-
- H—ELECTRICITY
- H01—BASIC ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
-
- H—ELECTRICITY
- H01—BASIC ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01029—Copper [Cu]
-
- H—ELECTRICITY
- H01—BASIC ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01006—Carbon [C]
-
- H—ELECTRICITY
- H01—BASIC ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/146—Mixed devices
- H01L2924/1461—MEMS
-
- H—ELECTRICITY
- H01—BASIC ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01033—Arsenic [As]
-
- H—ELECTRICITY
- H01—BASIC ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01079—Gold [Au]
-
- H—ELECTRICITY
- H01—BASIC ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/013—Alloys
-
- H—ELECTRICITY
- H01—BASIC ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01013—Aluminum [Al]
-
- H—ELECTRICITY
- H01—BASIC ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
-
- H—ELECTRICITY
- H01—BASIC ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
-
- H—ELECTRICITY
- H01—BASIC ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
-
- H—ELECTRICITY
- H01—BASIC ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
Similar Documents
Publication | Publication Date | Title |
---|---|---|
Shigetou et al. | Bumpless interconnect through ultrafine Cu electrodes by means of surface-activated bonding (SAB) method | |
US7022609B2 (en) | Manufacturing method of a semiconductor substrate provided with a through hole electrode | |
KR100313706B1 (en) | Redistributed Wafer Level Chip Size Package And Method For Manufacturing The Same | |
US4360142A (en) | Method of forming a solder interconnection capable of sustained high power levels between a semiconductor device and a supporting substrate | |
US6307261B1 (en) | Method for the manufacturing of a semiconductor device which comprises at least one chip and corresponding device | |
KR100426897B1 (en) | Fabrication and structure of solder terminal for flip chip packaging | |
CN109196638A (en) | Barrier layer for the interconnection piece in 3D integrated device | |
US4290079A (en) | Improved solder interconnection between a semiconductor device and a supporting substrate | |
US5092036A (en) | Ultra-tall indium or alloy bump array for IR detector hybrids and micro-electronics | |
CN114852948A (en) | MEMS sensor integrated device based on through silicon via and manufacturing method thereof | |
US6716669B2 (en) | High-density interconnection of temperature sensitive electronic devices | |
Dang et al. | Sea-of-leads MEMS I/O interconnects for low-k IC packaging | |
Pan et al. | Flip chip electrical interconnection by selective electroplating and bonding | |
Lim et al. | Process development and reliability of microbumps | |
Yoon et al. | Reliability of a silicon stacked module for 3-D SiP microsystem | |
Pan et al. | Batch transfer of LIGA microstructures by selective electroplating and bonding | |
Bakir et al. | Sea of leads compliant I/O interconnect process integration for the ultimate enabling of chips with low-k interlayer dielectrics | |
Kacker et al. | Electrical/Mechanical modeling, reliability assessment, and fabrication of FlexConnects: A MEMS-based compliant chip-to-substrate interconnect | |
Kacker et al. | Low-K dielectric compatible wafer-level compliant chip-to-substrate interconnects | |
Chow et al. | Wafer-level packaging with soldered stress-engineered micro-springs | |
Rao et al. | Design and development of fine pitch copper/low-k wafer level package | |
CN114877917A (en) | Thin film type sensor based on wafer level packaging and manufacturing method thereof | |
Joung | Electroplating bonding technology for chip interconnect, wafer level packaging and interconnect layer structures | |
Kacker et al. | Design and fabrication of flexconnects: A cost-effective implementation of compliant chip-to-substrate interconnects | |
Okereke et al. | Three-path electroplated copper compliant interconnects—Fabrication and modeling studies |